feat(igla): Wave Loop 764 — module-scope [347][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable

.claude/plans/wave-loop-764.md

@@ -12,15 +12,15 @@ field writes and `assert_eq` read-back in a `bench` block.
 
 ## PHI LOOP decomposition
 
-- [ ] **Issue** - Confirm #1735 scope and Variant A.
-- [ ] **Spec** - Generate `specs/scratch/w764_bench_module_347x2p6_aos_var_call_write.t27`.
-- [ ] **TDD** - Include `test` write schedule and `bench` read-back assertions.
-- [ ] **Impl** - No compiler changes; reuse W632 inner-dimension offset formula.
-- [ ] **Gen** - Run direct witness generation from `scripts/gen_w764.py`.
-- [ ] **Seal** - `t27c seal --save` the witness.
-- [ ] **Verify** - `parse`, `icarus-lowerable`, `icarus-simulate`, `icarus-cocotb`, cargo suites.
+- [x] **Issue** - Confirm #1735 scope and Variant A.
+- [x] **Spec** - Generate `specs/scratch/w764_bench_module_347x2p6_aos_var_call_write.t27`.
+- [x] **TDD** - Include `test` write schedule and `bench` read-back assertions.
+- [x] **Impl** - No compiler changes; reuse W632 inner-dimension offset formula.
+- [x] **Gen** - Run direct witness generation from `scripts/gen_w764.py`.
+- [x] **Seal** - `t27c seal --save` the witness.
+- [x] **Verify** - `parse`, `icarus-lowerable`, `icarus-simulate`, `icarus-cocotb`, cargo suites.
 - [ ] **Land** - Merge `wave-loop-764` to `master` with `Closes #1735`.
-- [ ] **Learn** - Save W764 memory + update `skills-wave-loop-recipe.md` + `MEMORY.md`.
+- [x] **Learn** - Save W764 memory + update `skills-wave-loop-recipe.md` + `MEMORY.md`.
 
 ## Three cooperation variants for next Wave Loop
 

.claude/plans/wave-loop-765.md

@@ -0,0 +1,38 @@
+# Wave Loop 765 Plan
+
+**Issue:** #1736
+**Branch:** `wave-loop-765`
+**Date:** 2026-07-23
+
+## Goal
+
+Close Wave Loop 765 by validating a module-scope `[349][2]^6 Pt` packed
+array-of-struct variable initialized from a function call, with indexed signed
+field writes and `assert_eq` read-back in a `bench` block.
+
+## PHI LOOP decomposition
+
+- [ ] **Issue** - Confirm #1736 scope and Variant A.
+- [ ] **Spec** - Generate `specs/scratch/w765_bench_module_349x2p6_aos_var_call_write.t27`.
+- [ ] **TDD** - Include `test` write schedule and `bench` read-back assertions.
+- [ ] **Impl** - No compiler changes; reuse W632 inner-dimension offset formula.
+- [ ] **Gen** - Run direct witness generation from `scripts/gen_w765.py`.
+- [ ] **Seal** - `t27c seal --save` the witness.
+- [ ] **Verify** - `parse`, `icarus-lowerable`, `icarus-simulate`, `icarus-cocotb`, cargo suites.
+- [ ] **Land** - Merge `wave-loop-765` to `master` with `Closes #1736`.
+- [ ] **Learn** - Save W765 memory + update `skills-wave-loop-recipe.md` + `MEMORY.md`.
+
+## Three cooperation variants for next Wave Loop
+
+1. **Variant A (recommended):** continue the odd outer-dimension ladder with `[351][2]^6 Pt`.
+2. **Variant B:** keep width at ~0.682 MiBit but move the packed var to bench/function scope.
+3. **Variant C:** add `if`-guarded indexed signed field writes at the current width.
+
+## Definition of done
+
+All acceptance criteria in `.trinity/current-issue.md` are green and the
+closeout report is written to `docs/reports/FPGA_LOOP_CLOSEOUT_W765_2026-07-23.md`.
+
+---
+
+phi^2 + 1/phi^2 = 3 | TRINITY

.trinity/current-issue.md

@@ -1,45 +1,45 @@
-# Wave Loop 764 — Issue #1735
+# Wave Loop 765 — Issue #1736
 
-**Branch:** `wave-loop-764`  
+**Branch:** `wave-loop-765`  
 **Date:** 2026-07-23  
 **Cooperation variant:** A (recommended)
 
 ## Goal
 
-Close Wave Loop 764 by validating a module-scope `[347][2]^6 Pt` packed
+Close Wave Loop 765 by validating a module-scope `[349][2]^6 Pt` packed
 array-of-struct variable initialized from a function call, with indexed signed
 field writes and `assert_eq` read-back in a `bench` block.
 
 ## Acceptance criteria
 
-1. `specs/scratch/w764_bench_module_347x2p6_aos_var_call_write.t27` is generated and parses.
+1. `specs/scratch/w765_bench_module_349x2p6_aos_var_call_write.t27` is generated and parses.
 2. The witness is Icarus-lowerable and simulates correctly (17 cycles, PASSED).
 3. The cocotb reference model matches the t27 semantics.
 4. `t27c seal --save` succeeds and FROZEN_HASH remains unchanged.
 5. All cargo suites remain green.
-6. Integration test `accepts_w764_bench_module_347x2p6_aos_var_call_write` is added.
-7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W764_2026-07-23.md` is written.
+6. Integration test `accepts_w765_bench_module_349x2p6_aos_var_call_write` is added.
+7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W765_2026-07-23.md` is written.
 8. Learning is saved to `.trinity/experience.md`, memory, and `skills-wave-loop-recipe.md`.
-9. Branch merges to `master` with `Closes #1735`.
+9. Branch merges to `master` with `Closes #1736`.
 
 ## Technical notes
 
-- Shape: `[347][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
-- Total elements: `347 × 64 = 22,208`.
-- Packed vector width: `22,208 × 32 = 710,656` bits (~0.678 MiBit).
-- `MID_IDX = 173`; frame-condition element `[173][1][0][0][0][0][0]` is element
-  `173*64 + 32 = 11,104`.
-- Generator script: `scripts/gen_w764.py` (copy from `scripts/gen_w763.py`, set
-  `OUTER = 347` and `MID_IDX = 173`, manually fix the f-string header).
+- Shape: `[349][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
+- Total elements: `349 × 64 = 22,336`.
+- Packed vector width: `22,336 × 32 = 714,752` bits (~0.682 MiBit).
+- `MID_IDX = 174`; frame-condition element `[174][1][0][0][0][0][0]` is element
+  `174*64 + 32 = 11,168`.
+- Generator script: `scripts/gen_w765.py` (copy from `scripts/gen_w764.py`, set
+  `OUTER = 349` and `MID_IDX = 174`, manually fix the f-string header).
 - Use `assert_eq` checks on changed elements (Icarus simulation path does not
   emit `assert_ne`).
 - Include `make_grid(32768)` period-identity check because `32768 ≡ 0 (mod 32768)`.
 - Zero compiler / reference-model / FROZEN_HASH changes expected.
 
 ## Cooperation variants for next Wave Loop
 
-- **Variant A (recommended):** continue the odd outer-dimension ladder with `[349][2]^6 Pt`.
-- **Variant B:** keep width at ~0.678 MiBit but move the packed var to bench/function scope.
+- **Variant A (recommended):** continue the odd outer-dimension ladder with `[351][2]^6 Pt`.
+- **Variant B:** keep width at ~0.682 MiBit but move the packed var to bench/function scope.
 - **Variant C:** add `if`-guarded indexed signed field writes at the current width.
 
 ---

.trinity/experience.md

@@ -1,3 +1,73 @@
+## 2026-07-23 — Wave Loop 764 (module-scope `[347][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
+
+### What worked
+- Variant A extended the module-scope packed AoS odd outer-dimension ladder to 347.
+  The `[347][2]^6 Pt` witness is 710,656 bits (~0.678 MiBit), still well under the 4-MiBit
+  cliff, and required no compiler changes.
+- A module-level `pub var dst : [347][2]^6 Pt` can be initialized from a function
+  call and exercised with indexed signed field writes, with zero compiler changes.
+- The cocotb/Python reference model correctly mirrored the row-major flattening
+  with outer stride 347, confirming the layout is preserved end-to-end.
+- Reused the corrected W632 element-index formula for mid-row expected values:
+  `[r][a5][a4][a3][a2][a1][a0]` is element `r*64 + a5*32 + a4*16 + a3*8 + a2*4 + a1*2 + a0`.
+- For `OUTER = 347`, `MID_IDX = 173`; the frame-condition element is
+  `[173][1][0][0][0][0][0]`, element number `173*64 + 32 = 11,104`.
+- Updated weak-point audit: 576 commits in 30 days (29 with `Closes #N`), 57
+  `.t27` specs without `test`/`invariant`/`bench`, 23 `scripts/*.sh` under `scripts/`.
+
+### What changed behavior
+- No changes to `bootstrap/src/compiler.rs`.
+- No changes to `bootstrap/stage0/FROZEN_HASH`.
+- No changes to `scripts/cocotb_ref_model.py`.
+- Added `specs/scratch/w764_bench_module_347x2p6_aos_var_call_write.t27` (~1,519 KB /
+  ~65,991 lines) with seal and Icarus baseline.
+- Added integration test `accepts_w764_bench_module_347x2p6_aos_var_call_write`.
+- Added generator script `scripts/gen_w764.py`.
+
+### Validation
+- `cargo build --release -p t27c`: OK.
+- `cargo test -p t27c --bin t27c`: 1494 passed; 0 failed; 2 ignored.
+- `cargo test -p tri`: 78 passed; 0 failed.
+- `cargo test -p t27c --test icarus_lowerable`: 224 passed; 0 failed.
+- Direct `t27c parse` W764: PASS.
+- Direct `t27c icarus-lowerable` W764: PASS (`lowerable`).
+- Direct `t27c icarus-simulate` W764: PASS (17 cycles, PASSED).
+- Direct `t27c icarus-cocotb` W764: PASS (`reference-model OK`).
+
+### Scientific / engineering background
+- IEEE 1800-2017 7.4.1/7.4.3 define packed-array total width as the product of
+  packed dimensions, with no power-of-two restriction. Variant A emits a single
+  710,656-bit packed vector, which is legal SystemVerilog.
+- Lutsig verified array lowering and CIRCT `HWLegalizeModules` show that
+  flattening nested arrays to wide packed vectors is a well-founded compiler
+  discipline, even when outer dimensions are non-power-of-two.
+- Icarus issue #1134 documents assertion failures for unpacked arrays of packed
+  structs; t27 scalar flattening avoids that construct entirely.
+- Yosys issue #2677 / #4653 confirm that arrays of packed structs remain
+  unsupported in the native frontend; t27 packed-vector lowering avoids the
+  gap.
+- 2025-2026 ternary/MVL literature scan found:
+  - Trinity B002 / Trinity v2.0.x — zero-DSP ternary-weight autoregressive LLM
+    inference on Xilinx Artix-7 via OpenXC7, ~63 tok/s @ ~1 W, QMTech XC7A100T
+    (Zenodo 2025/2026).
+  - TerEffic — highly efficient ternary LLM inference on AMD Alveo U280, 16,300
+    tok/s on 370 M model, 455 tok/s/W (arXiv 2025).
+  - TeLLMe v2 — end-to-end ternary LLM prefill/decode accelerator on AMD Kria
+    KV260, up to 25 tok/s decode / 143 tok/s prefill under 5 W (arXiv 2025).
+  - 5500FP / GargantuRAM — 24-trit balanced ternary RISC processor on Efinix
+    Trion FPGA at 20 MHz, real ±3.3 V ternary I/O, CERN-OHL-P v2 board,
+    commercially available (Zenodo/GitHub/Hackaday 2026).
+  - TernaryCore — open-source native {-1,0,+1} Verilog BitNet b1.58 accelerator,
+    zero DSP, 31/31 simulations passing, Artix-7 roadmap (GitHub 2026).
+  - Unbalanced ternary full adder in CNTFET — 42-transistor design with 35.8–75.2%
+    power reduction (IEEE TCAD 2026).
+  - CNTFET-based ternary full adder — 76/55 CNTFET complete/partial adders with
+    ~24% delay improvement (IEEE TCAD 2025).
+  - Energy-optimized ternary full adder using capacitive threshold logic and
+    CNTFETs for DSP (AEU 2026).
+  - OpenXC7 / nextpnr-xilinx / Project X-Ray — fully open-source Xilinx
+    7-series toolchain, used for QMTech XC7A100T ternary projects without Vivado.
+
 ## 2026-07-23 — Wave Loop 763 (module-scope `[345][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
 
 ### What worked

.trinity/seals/scratch_w764_bench_module_347x2p6_aos_var_call_write.json

@@ -0,0 +1,11 @@
+{
+  "gen_hash_c": "sha256:b64f43244e6a9d225d5a7327572442f57344e06f60d50ce9fa676d547247f307",
+  "gen_hash_rust": "sha256:663a8317ecd50fd02d30d36d926a1fb332fdd940aca2dfd1865b8449f5a99d72",
+  "gen_hash_verilog": "sha256:e3457fd0373185241902a443973ca60d8e1257d11c7ed21643ebfdcde8d1dba7",
+  "gen_hash_zig": "sha256:3429f41cd60d56362e519bc26e4fb2e71f3b4e7fc8501f901aed3cb526ee1acb",
+  "module": "w764_bench_module_347x2p6_aos_var_call_write",
+  "ring": 12,
+  "sealed_at": "2026-07-23T16:54:36Z",
+  "spec_hash": "sha256:f6a77109ee9a4fcf3b48dd1a9f7e7def307c916304459969e236c18006b0f37e",
+  "spec_path": "specs/scratch/w764_bench_module_347x2p6_aos_var_call_write.t27"
+}

bootstrap/tests/icarus_lowerable.rs

@@ -4045,6 +4045,24 @@ fn accepts_w763_bench_module_345x2p6_aos_var_call_write() {
     }
 }
 
+#[test]
+fn accepts_w764_bench_module_347x2p6_aos_var_call_write() {
+    let dir = scratch_dir();
+    for name in &[
+        "w764_bench_module_347x2p6_aos_var_call_write.t27",
+    ] {
+        let p = dir.join(name);
+        assert!(p.exists(), "missing W764 witness {}", p.display());
+        let (lowerable, json) = run_icarus_lowerable(&p);
+        assert!(
+            lowerable,
+            "expected {} to be lowerable, got: {}",
+            p.display(),
+            json
+        );
+    }
+}
+
 #[test]
 fn accepts_known_lowerable_witnesses() {
     let dir = scratch_dir();

docs/NOW.md

@@ -1,28 +1,28 @@
-# NOW — Wave Loop 763 close-out / Wave Loop 764 setup (2026-07-23)
+# NOW — Wave Loop 764 close-out / Wave Loop 765 setup (2026-07-23)
 
 Last updated: 2026-07-23
 
-## Wave Loop 763 — module-scope `[345][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1734)
+## Wave Loop 764 — module-scope `[347][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1735)
 
-- Branch: `wave-loop-763`
-- Issue: #1734
-- PR: #1471
-- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W763_2026-07-23.md`
-- Plan: `.claude/plans/wave-loop-763.md`
-- Cooperation W764: `.claude/plans/wave-loop-764.md`
+- Branch: `wave-loop-764`
+- Issue: #1735
+- PR: to open
+- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W764_2026-07-23.md`
+- Plan: `.claude/plans/wave-loop-764.md`
+- Cooperation W765: `.claude/plans/wave-loop-765.md`
 
 ### What landed
-- `specs/scratch/w763_bench_module_345x2p6_aos_var_call_write.t27`
-  - 22,080 elements, 706,560-bit packed vector (~0.674 MiBit).
-  - Module-scope `pub var dst : [345][2]^6 Pt` initialized from a function call and
+- `specs/scratch/w764_bench_module_347x2p6_aos_var_call_write.t27`
+  - 22,208 elements, 710,656-bit packed vector (~0.678 MiBit).
+  - Module-scope `pub var dst : [347][2]^6 Pt` initialized from a function call and
     exercised with indexed signed field writes.
   - `assert_eq` read-back in a `bench` block (Icarus path does not emit `assert_ne`).
-- `scripts/gen_w763.py`
-  - Generator for the W763 witness; `OUTER = 345`, `MID_IDX = 172`.
+- `scripts/gen_w764.py`
+  - Generator for the W764 witness; `OUTER = 347`, `MID_IDX = 173`.
 - `bootstrap/tests/icarus_lowerable.rs`
-  - Added `accepts_w763_bench_module_345x2p6_aos_var_call_write`.
-- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-764.md`
-  - W763 learnings saved and W764 issue/plan created.
+  - Added `accepts_w764_bench_module_347x2p6_aos_var_call_write`.
+- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-765.md`
+  - W764 learnings saved and W765 issue/plan created.
 
 ### Not changed
 - `bootstrap/src/compiler.rs` — zero compiler changes.
@@ -33,8 +33,21 @@ Last updated: 2026-07-23
 - `cargo build --release -p t27c`: OK.
 - `cargo test -p t27c --bin t27c`: 1494/0/2.
 - `cargo test -p tri`: 78/0.
-- `cargo test -p t27c --test icarus_lowerable`: 223/0.
-- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W763: PASS.
+- `cargo test -p t27c --test icarus_lowerable`: 224/0.
+- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W764: PASS.
+
+---
+
+## Wave Loop 765 — next odd outer-dimension `[349][2]^6 Pt` (Issue #1736)
+
+- Branch: `wave-loop-765` (to create after W764 merge)
+- Issue: #1736
+- Plan: `.claude/plans/wave-loop-765.md`
+
+### Candidate variants
+- Variant A (recommended): continue the odd outer-dimension ladder with `[349][2]^6 Pt`.
+- Variant B: keep width at ~0.678 MiBit but move the packed var to bench/function scope.
+- Variant C: add `if`-guarded indexed signed field writes at the current width.
 
 ---