Wave Loop 767 — module-scope [353][2]^6 Pt AoS var from call with indexed signed writes

.claude/plans/wave-loop-768.md

@@ -0,0 +1,48 @@
+# Wave Loop 768 Plan — Issue #1739
+
+## Phase 1: Issue
+- Confirm W768 issue #1739 and branch `wave-loop-768`.
+
+## Phase 2: Spec
+- Generate `specs/scratch/w768_bench_module_355x2p6_aos_var_call_write.t27` using
+  `scripts/gen_w768.py` derived from `scripts/gen_w767.py`.
+- Constants: `OUTER = 355`, `TOTAL = 22720`, `LAST_IDX = 354`, `MID_IDX = 177`.
+
+## Phase 3: TDD
+- Inspect generated assertions: `make_grid(32768)`, `make_grid(1)`,
+  `call_write_grid`, field writes, `assert_eq` read-backs, mid and last checks.
+
+## Phase 4: Impl
+- Add integration test `accepts_w768_bench_module_355x2p6_aos_var_call_write` to
+  `bootstrap/tests/icarus_lowerable.rs`.
+
+## Phase 5: Gen
+- Run `cd bootstrap && cargo build --release -p t27c`.
+
+## Phase 6: Seal
+- Run `./bootstrap/target/release/t27c seal --save specs/scratch/w768_bench_module_355x2p6_aos_var_call_write.t27`.
+- Confirm FROZEN_HASH unchanged.
+
+## Phase 7: Verify
+- `./bootstrap/target/release/t27c parse ...`
+- `./bootstrap/target/release/t27c icarus-lowerable ...`
+- `./bootstrap/target/release/t27c icarus-simulate ...` (17 cycles)
+- `./bootstrap/target/release/t27c icarus-cocotb ...`
+- `cargo test -p t27c --bin t27c`
+- `cargo test -p tri`
+- `cargo test -p t27c --test icarus_lowerable`
+
+## Phase 8: Land
+- Commit with `feat(igla): Wave Loop 768 — module-scope [355][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1739)`.
+- Push `wave-loop-768`, open PR, merge to `master`, create `wave-loop-769`.
+
+## Phase 9: Learn
+- Write `docs/reports/FPGA_LOOP_CLOSEOUT_W768_2026-07-23.md`.
+- Save `.trinity/experience.md`, memory file, `MEMORY.md` pointer, and update
+  `skills-wave-loop-recipe.md`.
+
+## Cooperation variants for next Wave Loop
+
+- **A (recommended):** `[357][2]^6 Pt` (~0.698 MiBit), continuing the odd ladder.
+- **B:** move the packed variable to bench/function scope at the same width.
+- **C:** add conditional (`if`) indexed writes at the current width.

.trinity/current-issue.md

@@ -1,45 +1,45 @@
-# Wave Loop 766 — Issue #1737
+# Wave Loop 767 — Issue #1738
 
-**Branch:** `wave-loop-766`  
+**Branch:** `wave-loop-767`  
 **Date:** 2026-07-23  
 **Cooperation variant:** A (recommended)
 
 ## Goal
 
-Close Wave Loop 766 by validating a module-scope `[351][2]^6 Pt` packed
+Close Wave Loop 767 by validating a module-scope `[353][2]^6 Pt` packed
 array-of-struct variable initialized from a function call, with indexed signed
 field writes and `assert_eq` read-back in a `bench` block.
 
 ## Acceptance criteria
 
-1. `specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27` is generated and parses.
+1. `specs/scratch/w767_bench_module_353x2p6_aos_var_call_write.t27` is generated and parses.
 2. The witness is Icarus-lowerable and simulates correctly (17 cycles, PASSED).
 3. The cocotb reference model matches the t27 semantics.
 4. `t27c seal --save` succeeds and FROZEN_HASH remains unchanged.
 5. All cargo suites remain green.
-6. Integration test `accepts_w766_bench_module_351x2p6_aos_var_call_write` is added.
-7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W766_2026-07-23.md` is written.
+6. Integration test `accepts_w767_bench_module_353x2p6_aos_var_call_write` is added.
+7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W767_2026-07-23.md` is written.
 8. Learning is saved to `.trinity/experience.md`, memory, and `skills-wave-loop-recipe.md`.
-9. Branch merges to `master` with `Closes #1737`.
+9. Branch merges to `master` with `Closes #1738`.
 
 ## Technical notes
 
-- Shape: `[351][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
-- Total elements: `351 x 64 = 22,464`.
-- Packed vector width: `22,464 x 32 = 718,848` bits (~0.686 MiBit).
-- `MID_IDX = 175`; frame-condition element `[175][1][0][0][0][0][0]` is element
-  `175*64 + 32 = 11,232`.
-- Generator script: `scripts/gen_w766.py` (copy from `scripts/gen_w765.py`, set
-  `OUTER = 351` and `MID_IDX = 175`, manually fix the f-string header).
+- Shape: `[353][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
+- Total elements: `353 x 64 = 22,592`.
+- Packed vector width: `22,592 x 32 = 722,944` bits (~0.690 MiBit).
+- `MID_IDX = 176`; frame-condition element `[176][1][0][0][0][0][0]` is element
+  `176*64 + 32 = 11,296`.
+- Generator script: `scripts/gen_w767.py` (copy from `scripts/gen_w766.py`, set
+  `OUTER = 353` and `MID_IDX = 176`, manually fix the f-string header).
 - Use `assert_eq` checks on changed elements (Icarus simulation path does not
   emit `assert_ne`).
 - Include `make_grid(32768)` period-identity check because `32768 == 0 (mod 32768)`.
 - Zero compiler / reference-model / FROZEN_HASH changes expected.
 
 ## Cooperation variants for next Wave Loop
 
-- **Variant A (recommended):** continue the odd outer-dimension ladder with `[353][2]^6 Pt`.
-- **Variant B:** keep width at ~0.686 MiBit but move the packed var to bench/function scope.
+- **Variant A (recommended):** continue the odd outer-dimension ladder with `[355][2]^6 Pt`.
+- **Variant B:** keep width at ~0.690 MiBit but move the packed var to bench/function scope.
 - **Variant C:** add `if`-guarded indexed signed field writes at the current width.
 
 ---

.trinity/current_task/activity.md

@@ -3676,3 +3676,7 @@
 - **Commit:** feat(igla): Wave Loop 765 — module-scope [349][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1736)
 - **Files:** .claude/plans/wave-loop-767.md,.trinity/current-issue.md,.trinity/experience.md,.trinity/seals/scratch_w766_bench_module_351x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/NOW.md,docs/reports/FPGA_LOOP_CLOSEOUT_W766_2026-07-23.md,scripts/gen_w766.py,specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27
 
+## 2026-07-23T17:52:18Z — wave-loop-767
+- **Commit:** feat(igla): Wave Loop 766 — module-scope [351][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1737)
+- **Files:** .claude/plans/wave-loop-768.md,.trinity/current-issue.md,.trinity/experience.md,.trinity/seals/scratch_w767_bench_module_353x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/NOW.md,docs/reports/FPGA_LOOP_CLOSEOUT_W767_2026-07-23.md,scripts/gen_w767.py,specs/scratch/w767_bench_module_353x2p6_aos_var_call_write.t27
+

.trinity/experience.md

@@ -77,6 +77,84 @@
 
 ---
 
+## 2026-07-23 — Wave Loop 767 (module-scope `[353][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
+
+### What worked
+- Variant A extended the module-scope packed AoS odd outer-dimension ladder to 353.
+  The `[353][2]^6 Pt` witness is 722,944 bits (~0.690 MiBit), still well under the 4-MiBit
+  cliff, and required no compiler changes.
+- A module-level `pub var dst : [353][2]^6 Pt` can be initialized from a function
+  call and exercised with indexed signed field writes, with zero compiler changes.
+- The cocotb/Python reference model correctly mirrored the row-major flattening
+  with outer stride 353, confirming the layout is preserved end-to-end.
+- Reused the corrected W632 element-index formula for mid-row expected values:
+  `[r][a5][a4][a3][a2][a1][a0]` is element `r*64 + a5*32 + a4*16 + a3*8 + a2*4 + a1*2 + a0`.
+- For `OUTER = 353`, `MID_IDX = 176`; the frame-condition element is
+  `[176][1][0][0][0][0][0]`, element number `176*64 + 32 = 11,296`.
+- Updated weak-point audit: 41 of 50 30-day commits include `Closes #N` (≈82%).
+  Clean non-worktree scan: 53 of 894 `.t27` specs lack `test`/`invariant`/`bench`
+  (≈5.9%). 19 `scripts/*.sh` remain under `scripts/`.
+- Fresh 2025-2026 literature scan surfaced memristor/RAM ternary logic,
+  MVL FPGA architectures, ternary RTL-to-netlist synthesis, ternary VHDL,
+  ternary public-key cryptography, and ternary LWE cryptanalysis.
+
+### What changed behavior
+- No changes to `bootstrap/src/compiler.rs`.
+- No changes to `bootstrap/stage0/FROZEN_HASH`.
+- No changes to `scripts/cocotb_ref_model.py`.
+- Added `specs/scratch/w767_bench_module_353x2p6_aos_var_call_write.t27` (~1,545 KB /
+  ~67,131 lines) with seal and Icarus baseline.
+- Added integration test `accepts_w767_bench_module_353x2p6_aos_var_call_write`.
+- Added generator script `scripts/gen_w767.py`.
+
+### Validation
+- `cargo build --release -p t27c`: OK.
+- `cargo test -p t27c --bin t27c`: 1494 passed; 0 failed; 2 ignored.
+- `cargo test -p tri`: 78 passed; 0 failed.
+- `cargo test -p t27c --test icarus_lowerable`: 227 passed; 0 failed.
+- Direct `t27c parse` W767: PASS.
+- Direct `t27c icarus-lowerable` W767: PASS (`lowerable`).
+- Direct `t27c icarus-simulate` W767: PASS (17 cycles, PASSED).
+- Direct `t27c icarus-cocotb` W767: PASS (`reference-model OK`).
+
+### Scientific / engineering background
+- IEEE 1800-2017 7.4.1/7.4.3 define packed-array total width as the product of
+  packed dimensions, with no power-of-two restriction. Variant A emits a single
+  722,944-bit packed vector, which is legal SystemVerilog.
+- Lutsig verified array lowering and CIRCT `HWLegalizeModules` show that
+  flattening nested arrays to wide packed vectors is a well-founded compiler
+  discipline, even when outer dimensions are non-power-of-two.
+- Icarus issue #1134 documents assertion failures for unpacked arrays of packed
+  structs; t27 scalar flattening avoids that construct entirely.
+- Yosys issue #2677 / #4653 confirm that arrays of packed structs remain
+  unsupported in the native frontend; t27 packed-vector lowering avoids the
+  gap.
+- 2025-2026 ternary/MVL literature scan found:
+  - Multi-Level Resistive Synapses — memristive crossbar fabric with ternary
+    BitNet datapath using differential memristor pairs (arXiv 2026).
+  - TerEffic — Alveo U280 ternary LLM accelerator, 16,300 tok/s at 455 tok/s/W
+    for 370M model (arXiv 2025).
+  - In-memory balanced ternary gates/decoders via tri-valued memristors
+    (EPJ Plus 2026).
+  - Ternary Łukasiewicz logic in 1T1R ReRAM crossbar, experimentally validated
+    on commercial 200 mm chip (Phil. Trans. R. Soc. A 2025).
+  - Tri-state memristor ternary NOT/NAND/NOR and cascaded decoder in 3D crossbar
+    (Adv. Electron. Mater. 2025).
+  - Generalized T-gate based MVL FPGA architecture merging LUT and flip-flop
+    functions (IEEE Access 2025).
+  - Tlsys — first ternary RTL-to-CNFET netlist synthesis framework, >500k gates
+    (Chinese Journal of Electronics 2026).
+  - Ternary VHDL extension TVHDL for mixed-radix VLSI simulation with GHDL/GTKWave
+    (IEEE ISMVL 2026).
+  - Ternary public-key cryptosystem using ternary group rings and matrix
+    ternarization (arXiv 2026).
+  - Ternary LWE key-search via quantum-walk LSH attack, concrete security
+    estimates for NTRU/BLISS/GLP (MDPI Information 2025).
+  - OpenXC7 / nextpnr-xilinx / Project X-Ray — fully open-source Xilinx
+    7-series toolchain, used for QMTech XC7A100T ternary projects without Vivado.
+
+---
+
 ## 2026-07-23 — Wave Loop 766 (module-scope `[351][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
 
 ### What worked

.trinity/seals/scratch_w767_bench_module_353x2p6_aos_var_call_write.json

@@ -0,0 +1,11 @@
+{
+  "gen_hash_c": "sha256:92a9cede78ec66dd3d2106434efa366d08612e3360b9b94341d1fb87ed9d21ac",
+  "gen_hash_rust": "sha256:e35e12f899d8dcbd801fc1d4f678dfb9d16364ff0fe1c5087754a61f9d0e09a7",
+  "gen_hash_verilog": "sha256:6bc1637150fbd431af3c00fea524897cbfcb36d2aadc511550c1e78a1bef35b0",
+  "gen_hash_zig": "sha256:2cd31441d1682b6b672ee97e8d51cb973230948efb77b43d130ef256d2833e16",
+  "module": "w767_bench_module_353x2p6_aos_var_call_write",
+  "ring": 12,
+  "sealed_at": "2026-07-23T17:43:48Z",
+  "spec_hash": "sha256:55d934712dfd831e69f74639a117dfe42f93b0db5ee66352c7f221e2860acc27",
+  "spec_path": "specs/scratch/w767_bench_module_353x2p6_aos_var_call_write.t27"
+}

bootstrap/tests/icarus_lowerable.rs

@@ -4099,6 +4099,24 @@ fn accepts_w766_bench_module_351x2p6_aos_var_call_write() {
     }
 }
 
+#[test]
+fn accepts_w767_bench_module_353x2p6_aos_var_call_write() {
+    let dir = scratch_dir();
+    for name in &[
+        "w767_bench_module_353x2p6_aos_var_call_write.t27",
+    ] {
+        let p = dir.join(name);
+        assert!(p.exists(), "missing W767 witness {}", p.display());
+        let (lowerable, json) = run_icarus_lowerable(&p);
+        assert!(
+            lowerable,
+            "expected {} to be lowerable, got: {}",
+            p.display(),
+            json
+        );
+    }
+}
+
 #[test]
 fn accepts_known_lowerable_witnesses() {
     let dir = scratch_dir();

docs/NOW.md

@@ -1,28 +1,28 @@
-# NOW — Wave Loop 766 close-out / Wave Loop 767 setup (2026-07-23)
+# NOW — Wave Loop 767 close-out / Wave Loop 768 setup (2026-07-23)
 
 Last updated: 2026-07-23
 
-## Wave Loop 766 — module-scope `[351][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1737)
+## Wave Loop 767 — module-scope `[353][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1738)
 
-- Branch: `wave-loop-766`
-- Issue: #1737
+- Branch: `wave-loop-767`
+- Issue: #1738
 - PR: to open
-- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W766_2026-07-23.md`
-- Plan: `.claude/plans/wave-loop-766.md`
-- Cooperation W767: `.claude/plans/wave-loop-767.md`
+- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W767_2026-07-23.md`
+- Plan: `.claude/plans/wave-loop-767.md`
+- Cooperation W768: `.claude/plans/wave-loop-768.md`
 
 ### What landed
-- `specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27`
-  - 22,464 elements, 718,848-bit packed vector (~0.686 MiBit).
-  - Module-scope `pub var dst : [351][2]^6 Pt` initialized from a function call and
+- `specs/scratch/w767_bench_module_353x2p6_aos_var_call_write.t27`
+  - 22,592 elements, 722,944-bit packed vector (~0.690 MiBit).
+  - Module-scope `pub var dst : [353][2]^6 Pt` initialized from a function call and
     exercised with indexed signed field writes.
   - `assert_eq` read-back in a `bench` block (Icarus path does not emit `assert_ne`).
-- `scripts/gen_w766.py`
-  - Generator for the W766 witness; `OUTER = 351`, `MID_IDX = 175`.
+- `scripts/gen_w767.py`
+  - Generator for the W767 witness; `OUTER = 353`, `MID_IDX = 176`.
 - `bootstrap/tests/icarus_lowerable.rs`
-  - Added `accepts_w766_bench_module_351x2p6_aos_var_call_write`.
-- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-767.md`
-  - W766 learnings saved and W767 issue/plan created.
+  - Added `accepts_w767_bench_module_353x2p6_aos_var_call_write`.
+- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-768.md`
+  - W767 learnings saved and W768 issue/plan created.
 
 ### Not changed
 - `bootstrap/src/compiler.rs` — zero compiler changes.
@@ -33,8 +33,21 @@ Last updated: 2026-07-23
 - `cargo build --release -p t27c`: OK.
 - `cargo test -p t27c --bin t27c`: 1494/0/2.
 - `cargo test -p tri`: 78/0.
-- `cargo test -p t27c --test icarus_lowerable`: 226/0.
-- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W766: PASS.
+- `cargo test -p t27c --test icarus_lowerable`: 227/0.
+- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W767: PASS.
+
+---
+
+## Wave Loop 768 — next odd outer-dimension `[355][2]^6 Pt` (Issue #1739)
+
+- Branch: `wave-loop-768` (to create after W767 merge)
+- Issue: #1739
+- Plan: `.claude/plans/wave-loop-768.md`
+
+### Candidate variants
+- Variant A (recommended): continue the odd outer-dimension ladder with `[355][2]^6 Pt`.
+- Variant B: keep width at ~0.690 MiBit but move the packed var to bench/function scope.
+- Variant C: add `if`-guarded indexed signed field writes at the current width.
 
 ---