Wave Loop 772 — [363][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes

.claude/plans/wave-loop-773.md

@@ -0,0 +1,48 @@
+# Wave Loop 773 Plan — Issue #1744
+
+## Phase 1: Issue
+- Confirm W773 issue #1744 and branch `wave-loop-773`.
+
+## Phase 2: Spec
+- Generate `specs/scratch/w773_bench_module_365x2p6_aos_var_call_write.t27` using
+  `scripts/gen_w773.py` derived from `scripts/gen_w772.py`.
+- Constants: `OUTER = 365`, `TOTAL = 23360`, `LAST_IDX = 364`, `MID_IDX = 182`.
+
+## Phase 3: TDD
+- Inspect generated assertions: `make_grid(32768)`, `make_grid(1)`,
+  `call_write_grid`, field writes, `assert_eq` read-backs, mid and last checks.
+
+## Phase 4: Impl
+- Add integration test `accepts_w773_bench_module_365x2p6_aos_var_call_write` to
+  `bootstrap/tests/icarus_lowerable.rs`.
+
+## Phase 5: Gen
+- Run `cd bootstrap && cargo build --release -p t27c`.
+
+## Phase 6: Seal
+- Run `./bootstrap/target/release/t27c seal --save specs/scratch/w773_bench_module_365x2p6_aos_var_call_write.t27`.
+- Confirm FROZEN_HASH unchanged.
+
+## Phase 7: Verify
+- `./bootstrap/target/release/t27c parse ...`
+- `./bootstrap/target/release/t27c icarus-lowerable ...`
+- `./bootstrap/target/release/t27c icarus-simulate ...` (17 cycles)
+- `./bootstrap/target/release/t27c icarus-cocotb ...`
+- `cargo test -p t27c --bin t27c`
+- `cargo test -p tri`
+- `cargo test -p t27c --test icarus_lowerable`
+
+## Phase 8: Land
+- Commit with `feat(igla): Wave Loop 773 — module-scope [365][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1744)`.
+- Push `wave-loop-773`, open PR, merge to `master`, create `wave-loop-774`.
+
+## Phase 9: Learn
+- Write `docs/reports/FPGA_LOOP_CLOSEOUT_W773_2026-07-24.md`.
+- Save `.trinity/experience.md`, memory file, `MEMORY.md` pointer, and update
+  `skills-wave-loop-recipe.md`.
+
+## Cooperation variants for next Wave Loop
+
+- **A (recommended):** `[367][2]^6 Pt` (~0.717 MiBit), continuing the odd ladder.
+- **B:** move the packed variable to bench/function scope at the same width.
+- **C:** add conditional (`if`) indexed writes at the current width.

.trinity/current-issue.md

@@ -1,45 +1,45 @@
-# Wave Loop 771 — Issue #1742
+# Wave Loop 772 — Issue #1743
 
-**Branch:** `wave-loop-771`  
+**Branch:** `wave-loop-772`  
 **Date:** 2026-07-24  
 **Cooperation variant:** A (recommended)
 
 ## Goal
 
-Close Wave Loop 771 by validating a module-scope `[361][2]^6 Pt` packed
+Close Wave Loop 772 by validating a module-scope `[363][2]^6 Pt` packed
 array-of-struct variable initialized from a function call, with indexed signed
 field writes and `assert_eq` read-back in a `bench` block.
 
 ## Acceptance criteria
 
-1. `specs/scratch/w771_bench_module_361x2p6_aos_var_call_write.t27` is generated and parses.
+1. `specs/scratch/w772_bench_module_363x2p6_aos_var_call_write.t27` is generated and parses.
 2. The witness is Icarus-lowerable and simulates correctly (17 cycles, PASSED).
 3. The cocotb reference model matches the t27 semantics.
 4. `t27c seal --save` succeeds and FROZEN_HASH remains unchanged.
 5. All cargo suites remain green.
-6. Integration test `accepts_w771_bench_module_361x2p6_aos_var_call_write` is added.
-7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W771_2026-07-24.md` is written.
+6. Integration test `accepts_w772_bench_module_363x2p6_aos_var_call_write` is added.
+7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W772_2026-07-24.md` is written.
 8. Learning is saved to `.trinity/experience.md`, memory, and `skills-wave-loop-recipe.md`.
-9. Branch merges to `master` with `Closes #1742`.
+9. Branch merges to `master` with `Closes #1743`.
 
 ## Technical notes
 
-- Shape: `[361][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
-- Total elements: `361 x 64 = 23,104`.
-- Packed vector width: `23,104 x 32 = 739,328` bits (~0.705 MiBit).
-- `MID_IDX = 180`; frame-condition element `[180][1][0][0][0][0][0]` is element
-  `180*64 + 32 = 11,552`.
-- Generator script: `scripts/gen_w771.py` (copy from `scripts/gen_w770.py`, set
-  `OUTER = 361` and `MID_IDX = 180`, manually fix the f-string header).
+- Shape: `[363][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
+- Total elements: `363 x 64 = 23,232`.
+- Packed vector width: `23,232 x 32 = 743,424` bits (~0.709 MiBit).
+- `MID_IDX = 181`; frame-condition element `[181][1][0][0][0][0][0]` is element
+  `181*64 + 32 = 11,616`.
+- Generator script: `scripts/gen_w772.py` (copy from `scripts/gen_w771.py`, set
+  `OUTER = 363` and `MID_IDX = 181`, manually fix the f-string header).
 - Use `assert_eq` checks on changed elements (Icarus simulation path does not
   emit `assert_ne`).
 - Include `make_grid(32768)` period-identity check because `32768 == 0 (mod 32768)`.
 - Zero compiler / reference-model / FROZEN_HASH changes expected.
 
 ## Cooperation variants for next Wave Loop
 
-- **Variant A (recommended):** continue the odd outer-dimension ladder with `[363][2]^6 Pt`.
-- **Variant B:** keep width at ~0.705 MiBit but move the packed var to bench/function scope.
+- **Variant A (recommended):** continue the odd outer-dimension ladder with `[365][2]^6 Pt`.
+- **Variant B:** keep width at ~0.709 MiBit but move the packed var to bench/function scope.
 - **Variant C:** add `if`-guarded indexed signed field writes at the current width.
 
 ---

.trinity/current_task/activity.md

@@ -3704,3 +3704,15 @@
 - **Commit:** feat(igla): Wave Loop 771 — module-scope [361][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1742)
 - **Files:** docs/NOW.md
 
+## 2026-07-23T18:53:45Z — wave-loop-772
+- **Commit:** feat(igla): Wave Loop 771 — module-scope [361][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1742)
+- **Files:** .trinity/current-issue.md
+
+## 2026-07-23T19:10:40Z — wave-loop-772
+- **Commit:** docs(trinity): Wave Loop 772 issue #1743 + branch wave-loop-772 created, next-wave cooperation variants set
+- **Files:** .trinity/experience.md,.trinity/seals/scratch_w772_bench_module_363x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/reports/FPGA_LOOP_CLOSEOUT_W772_2026-07-24.md,scripts/gen_w772.py,specs/scratch/w772_bench_module_363x2p6_aos_var_call_write.t27
+
+## 2026-07-23T19:12:48Z — wave-loop-772
+- **Commit:** feat(igla): Wave Loop 772 — module-scope [363][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes
+- **Files:** .claude/plans/wave-loop-773.md,docs/NOW.md
+

.trinity/experience.md

@@ -1,3 +1,92 @@
+## 2026-07-24 — Wave Loop 772 (module-scope `[363][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
+
+### What worked
+- Variant A extended the module-scope packed AoS odd outer-dimension ladder to 363.
+  The `[363][2]^6 Pt` witness is 743,424 bits (~0.709 MiBit), still well under the 4-MiBit
+  cliff, and required no compiler changes.
+- A module-level `pub var dst : [363][2]^6 Pt` can be initialized from a function
+  call and exercised with indexed signed field writes, with zero compiler changes.
+- The cocotb/Python reference model correctly mirrored the row-major flattening
+  with outer stride 363, confirming the layout is preserved end-to-end.
+- Reused the corrected W632 element-index formula for mid-row expected values:
+  `[r][a5][a4][a3][a2][a1][a0]` is element `r*64 + a5*32 + a4*16 + a3*8 + a2*4 + a1*2 + a0`.
+- For `OUTER = 363`, `MID_IDX = 181`; the frame-condition element is
+  `[181][1][0][0][0][0][0]`, element number `181*64 + 32 = 11,616`.
+- Updated weak-point audit: 10 of 57 30-day subject lines carry `Closes #N`/`Fixes #N`
+  on a subject-only scan, but merge/closeout commits contain the link in their body.
+  Clean non-worktree scan: 53 of ~903 `.t27` specs lack `test`/`invariant`/`bench`
+  (≈5.9%). 19 `scripts/*.sh` remain under `scripts/`.
+- Pre-existing FPGA synthesis/formal failures in CI (`sby` pip package missing,
+  Yosys static-cast Verilog-2005 limitation in `build/fpga/generated/uart.v`) are
+  unrelated to this wave and tracked as weak point #1245.
+- Fresh 2025-2026 literature scan reinforced IEEE 1800-2017 packed-array/struct
+  semantics (AMD UG900 2026.1, AR 51836) and ternary EDA/simulation work
+  (SONIC, TernaryCore, cocotb reference-model flows).
+
+### What changed behavior
+- No changes to `bootstrap/src/compiler.rs`.
+- No changes to `bootstrap/stage0/FROZEN_HASH`.
+- No changes to `scripts/cocotb_ref_model.py`.
+- Added `specs/scratch/w772_bench_module_363x2p6_aos_var_call_write.t27` (~1,590 KB /
+  ~69,031 lines) with seal and Icarus baseline.
+- Added integration test `accepts_w772_bench_module_363x2p6_aos_var_call_write`.
+- Added generator script `scripts/gen_w772.py`.
+
+### Validation
+- `cargo build --release -p t27c`: OK.
+- `cargo test -p t27c --bin t27c`: 1494 passed; 0 failed; 2 ignored.
+- `cargo test -p tri`: 78 passed; 0 failed.
+- `cargo test -p t27c --test icarus_lowerable`: 232 passed; 0 failed.
+- Direct `t27c parse` W772: PASS.
+- Direct `t27c icarus-lowerable` W772: PASS (`lowerable`).
+- Direct `t27c icarus-simulate` W772: PASS (17 cycles, PASSED).
+- Direct `t27c icarus-cocotb` W772: PASS (`reference-model OK`).
+
+### Scientific / engineering background
+- IEEE 1800-2017 7.4.1/7.4.3 define packed-array total width as the product of
+  packed dimensions, with no power-of-two restriction. Variant A emits a single
+  743,424-bit packed vector, which is legal SystemVerilog.
+- AMD UG900 2026.1 and AR 51836 confirm Vivado simulation/synthesis accept packed
+  arrays of structs as wide vectors, mapped to `svLogicVecVal` arrays in DPI.
+- Lutsig verified array lowering and CIRCT `HWLegalizeModules` show that
+  flattening nested arrays to wide packed vectors is a well-founded compiler
+  discipline, even when outer dimensions are non-power-of-two.
+- Icarus issue #1134 documents assertion failures for unpacked arrays of packed
+  structs; t27 scalar flattening avoids that construct entirely.
+- Yosys issue #2677 / #4653 confirm that arrays of packed structs remain
+  unsupported in the native frontend; t27 packed-vector lowering avoids the
+  gap.
+- 2025-2026 ternary/MVL literature scan found:
+  - TENET — sparsity-aware LUT-centric ternary LLM inference on FPGA and ASIC
+    (arXiv 2025).
+  - ELiTeFormer — hybrid linear attention + ternary projections for FPGAs
+    (arXiv 2026).
+  - KULeuven ternary-lut-dse — Chisel generator for LUT-based ternary MatMul,
+    accepted at IEEE ISPASS 2026.
+  - Tlsys — RTL-to-CNFET gate-level ternary synthesis framework with
+    verification methodology (Chinese Journal of Electronics 2026).
+  - Polynomial Surrogate Training — differentiable Kleene K₃ ternary logic gate
+    networks amenable to formal verification (arXiv 2026).
+  - Ternary Logic Encodings of Temporal Behavior Trees — Kleene strong ternary
+    semantics for STL/behavior trees with MILP/MIQP control synthesis
+    (arXiv 2026).
+  - SONIC — event-driven gate-level simulator/verifier for ternary VLSI circuits
+    using delta cycles (IEEE ISMVL 2026).
+  - CNTFET-based ternary LFSR/D-flip-flop design (Circuits Syst. Signal Process.
+    2026).
+  - Photonic multi-valued logic via Möbius phase-cycles and wavelength-division
+    ternary encoding (Zenodo 2026).
+  - All-optical photonic-crystal ternary inverters with nonlinear directional
+    couplers (Journal of Optical Communications 2026).
+  - OpenXC7 / nextpnr-xilinx / Project X-Ray — fully open-source Xilinx
+    7-series toolchain, used for QMTech XC7A100T ternary projects without Vivado.
+  - TernaryCore — open-source BitNet ternary FPGA accelerator simulated with
+    Icarus Verilog (GitHub 2026).
+  - cocotb reference-model + pyUVM flows for open-source ASIC/FPGA verification
+    (SyoSil 2024, DVCon EU 2025).
+
+---
+
 ## 2026-07-24 — Wave Loop 771 (module-scope `[361][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
 
 ### What worked

.trinity/seals/scratch_w772_bench_module_363x2p6_aos_var_call_write.json

@@ -0,0 +1,11 @@
+{
+  "gen_hash_c": "sha256:c2dafa6f73e6e4bccd1460a49196c5b4866ce330ceeaa52ac1df743ef0ca2693",
+  "gen_hash_rust": "sha256:c371976276791359200f2c9dbe8ba00bf4fc152435decaf26a455a75a3b2a5de",
+  "gen_hash_verilog": "sha256:be32508f36a5ceaf8cc9fb18599f0d77697c055674119662cf31aa2251880ad8",
+  "gen_hash_zig": "sha256:eb878b086da0ce369d119e83ab9c3c4f064351d200ef18802d4ba6e4af844790",
+  "module": "w772_bench_module_363x2p6_aos_var_call_write",
+  "ring": 12,
+  "sealed_at": "2026-07-23T19:02:16Z",
+  "spec_hash": "sha256:c8cab495ce62ff9b5e3cc485c2227f67f8e855fad8dfbb65e674a4864ed61aed",
+  "spec_path": "specs/scratch/w772_bench_module_363x2p6_aos_var_call_write.t27"
+}

bootstrap/tests/icarus_lowerable.rs

@@ -4189,6 +4189,24 @@ fn accepts_w771_bench_module_361x2p6_aos_var_call_write() {
     }
 }
 
+#[test]
+fn accepts_w772_bench_module_363x2p6_aos_var_call_write() {
+    let dir = scratch_dir();
+    for name in &[
+        "w772_bench_module_363x2p6_aos_var_call_write.t27",
+    ] {
+        let p = dir.join(name);
+        assert!(p.exists(), "missing W772 witness {}", p.display());
+        let (lowerable, json) = run_icarus_lowerable(&p);
+        assert!(
+            lowerable,
+            "expected {} to be lowerable, got: {}",
+            p.display(),
+            json
+        );
+    }
+}
+
 #[test]
 fn accepts_known_lowerable_witnesses() {
     let dir = scratch_dir();

docs/NOW.md

@@ -1,7 +1,56 @@
-# NOW — Wave Loop 771 close-out / Wave Loop 772 setup (2026-07-24)
+# NOW — Wave Loop 772 close-out / Wave Loop 773 setup (2026-07-24)
 
 Last updated: 2026-07-24
 
+## Wave Loop 772 — module-scope `[363][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1743)
+
+- Branch: `wave-loop-772`
+- Issue: #1743
+- PR: #1480
+- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W772_2026-07-24.md`
+- Plan: `.claude/plans/wave-loop-772.md`
+- Cooperation W773: `.claude/plans/wave-loop-773.md`
+
+### What landed
+- `specs/scratch/w772_bench_module_363x2p6_aos_var_call_write.t27`
+  - 23,232 elements, 743,424-bit packed vector (~0.709 MiBit).
+  - Module-scope `pub var dst : [363][2]^6 Pt` initialized from a function call and
+    exercised with indexed signed field writes.
+  - `assert_eq` read-back in a `bench` block (Icarus path does not emit `assert_ne`).
+- `scripts/gen_w772.py`
+  - Generator for the W772 witness; `OUTER = 363`, `MID_IDX = 181`.
+- `bootstrap/tests/icarus_lowerable.rs`
+  - Added `accepts_w772_bench_module_363x2p6_aos_var_call_write`.
+- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-773.md`
+  - W772 learnings saved and W773 issue/plan created.
+
+### Not changed
+- `bootstrap/src/compiler.rs` — zero compiler changes.
+- `bootstrap/stage0/FROZEN_HASH` — unchanged `68a0b933c00ba5efd7facb5997f00880c3eecae55e6ac5e8cea2aee399b92adc`.
+- `scripts/cocotb_ref_model.py` — unchanged.
+
+### Verification
+- `cargo build --release -p t27c`: OK.
+- `cargo test -p t27c --bin t27c`: 1494/0/2.
+- `cargo test -p tri`: 78/0.
+- `cargo test -p t27c --test icarus_lowerable`: 232/0.
+- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W772: PASS.
+
+---
+
+## Wave Loop 773 — next odd outer-dimension `[365][2]^6 Pt` (Issue #1744)
+
+- Branch: `wave-loop-773` (to create after W772 merge)
+- Issue: #1744
+- Plan: `.claude/plans/wave-loop-773.md`
+
+### Candidate variants
+- Variant A (recommended): continue the odd outer-dimension ladder with `[365][2]^6 Pt`.
+- Variant B: keep width at ~0.709 MiBit but move the packed var to bench/function scope.
+- Variant C: add `if`-guarded indexed signed field writes at the current width.
+
+---
+
 ## Wave Loop 771 — module-scope `[361][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1742)
 
 - Branch: `wave-loop-771`
@@ -38,19 +87,6 @@ Last updated: 2026-07-24
 
 ---
 
-## Wave Loop 772 — next odd outer-dimension `[363][2]^6 Pt` (Issue #1743)
-
-- Branch: `wave-loop-772` (to create after W771 merge)
-- Issue: #1743
-- Plan: `.claude/plans/wave-loop-772.md`
-
-### Candidate variants
-- Variant A (recommended): continue the odd outer-dimension ladder with `[363][2]^6 Pt`.
-- Variant B: keep width at ~0.705 MiBit but move the packed var to bench/function scope.
-- Variant C: add `if`-guarded indexed signed field writes at the current width.
-
----
-
 ## Wave Loop 770 — module-scope `[359][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1741)
 
 - Branch: `wave-loop-770`