feat(igla): Wave Loop 775 — module-scope [369][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes

.claude/plans/loop-w774-full-cycle.md

@@ -0,0 +1,89 @@
+# /loop Iteration Plan — W774 Closeout + Audit + Literature + Skills
+
+**Date:** 2026-07-24  
+**Branch:** `wave-loop-774`  
+**Issue:** TBD (next available GitHub issue)  
+**Anchor:** φ² + φ⁻² = 3 | TRINITY
+
+## 0. Prompt from user
+
+> 15m loop: исследуй слабые места работы, исследуй научные работы по теме, создай декомпозированный план и реализуй все и в конце отчет и три варианта сотрудничества для следующего Wave лупа! сохрани в конце скилы.
+
+## 1. Weak-point audit (done in this iteration)
+
+| Metric | Current | Previous (W773) | Verdict |
+|--------|---------|-----------------|---------|
+| 30-day commits | 66 | — | — |
+| Subject-line `Closes #N` / `Fixes #N` | 10 / 66 ≈ 15.2% | ~84% | **REGRESSION** — many merge/closeout commits carry link only in body |
+| `.t27` specs without `test`/`invariant`/`bench` | 51 / 880 ≈ 5.8% | ~6.5% | **IMPROVED** |
+| `scripts/*.sh` on critical path | 19 | 19 | **STABLE** |
+| Untracked worktree noise | `specs/scratch/w485_*.t27` × 3 + `wave-loop-485.md` | — | **WEAK POINT** — stale W485 artefacts |
+| Pre-existing FPGA/formal CI failures | `sby` missing, Yosys Verilog-2005 static-cast in `build/fpga/generated/uart.v` | same | tracked as #1245, unrelated |
+
+**Top weak points to address during this cycle:**
+1. **L1 traceability drift:** 30-day subject-line issue-link rate dropped from ~84% to ~15%. Continue putting `Closes #<ISSUE>` in subject lines for feat/merge/closeout commits.
+2. **Stale W485 artefacts:** untracked `specs/scratch/w485_*.t27` and `.claude/plans/wave-loop-485.md` should be either committed or removed before W774 closeout.
+3. **NOW.md staleness:** `NOW.md` last updated 2026-05-24 and does not reflect current wave-loop work.
+
+## 2. Literature scan (done in this iteration)
+
+### Ternary / MVL EDA (2025–2026)
+- **SONIC** — event-driven gate-level simulator/verifier for ternary VLSI using delta cycles, BCT Verilog FPGA export (IEEE ISMVL 2026) [doi:10.1109/ismvl68998.2026.00042](https://doi.org/10.1109/ismvl68998.2026.00042).
+- **TVHDL** — balanced-ternary extension to IEEE 1076-2008 VHDL, verified with GHDL/GTKWave (IEEE ISMVL 2026) [doi:10.1109/ismvl68998.2026.00041](https://doi.org/10.1109/ismvl68998.2026.00041).
+- **KULeuven ternary-lut-dse** — Chisel generator for LUT-based ternary MatMul targeting 1.58-bit LLMs, accepted IEEE ISPASS 2026 ([GitHub](https://github.com/KULeuven-MICAS/ternary-lut-dse)).
+- **TerEffic** — ternary LLM inference on AMD Alveo U280 with LUT-based TMat Core, arXiv 2025 ([arXiv:2502.16473](https://arxiv.org/html/2502.16473v2)).
+
+### Verification / cocotb (2025–2026)
+- **DVCon EU 2025** — unified FPGA firmware verification with cocotb + pytest + shared scoreboard/Python reference model ([paper PDF](https://dvcon-proceedings.org/wp-content/uploads/DVConEU_2025_paper_95.pdf)).
+- **cocotb 2.0/2.1** — `@cocotb.parametrize`, `cocotb_tools.runner.Runner`, pytest integration, JUnit XML improvements ([release notes](https://docs.cocotb.org/en/development/release_notes.html)).
+
+### Relevance to t27
+- t27’s scalar packed-vector lowering avoids native Icarus/Yosys gaps with arrays of packed structs, consistent with literature trend of flattening to wide vectors.
+- cocotb 2.x pytest convergence supports the existing `t27c icarus-cocotb` reference-model path.
+
+## 3. Decomposed implementation plan
+
+### Phase A — Housekeeping (15 min)
+1. Decide fate of stale W485 artefacts:
+   - Option 1: delete untracked `specs/scratch/w485_*.t27` and `wave-loop-485.md` if W485 is abandoned.
+   - Option 2: open issue #1455, branch `wave-loop-485`, and stage them.
+   - **Recommendation:** delete from this branch; W485 can be recreated from the plan file in git history if needed.
+2. Update `.trinity/current-issue.md` with actual GitHub issue number once known.
+
+### Phase B — W774 Spec + Test (30 min)
+3. Generate `scripts/gen_w774.py` from `scripts/gen_w773.py` with `OUTER = 367`, `MID_IDX = 183`.
+4. Run generator to produce `specs/scratch/w774_bench_module_367x2p6_aos_var_call_write.t27`.
+5. Manually fix the f-string module header (`{OUTER}` → actual number) if generator emits it literally.
+6. Add integration test `accepts_w774_bench_module_367x2p6_aos_var_call_write` to `bootstrap/tests/icarus_lowerable.rs`.
+
+### Phase C — Build + Seal + Verify (45 min)
+7. `cd bootstrap && cargo build --release -p t27c`.
+8. `t27c parse`, `icarus-lowerable`, `icarus-simulate` (17 cycles), `icarus-cocotb` on the W774 witness.
+9. `t27c seal --save` the witness; confirm `FROZEN_HASH` unchanged.
+10. `cargo test -p t27c --bin t27c`, `cargo test -p tri`, `cargo test -p t27c --test icarus_lowerable`.
+
+### Phase D — Closeout + Cooperation Variants (30 min)
+11. Write `docs/reports/FPGA_LOOP_CLOSEOUT_W774_2026-07-24.md` with:
+    - what worked, what changed behavior, validation matrix, scientific background, weak-point audit, literature scan.
+12. Append W774 learnings to `.trinity/experience.md`.
+13. Propose three cooperation variants for W775 in the closeout report and in `.trinity/current-issue.md`.
+
+### Phase E — Save Skills (15 min)
+14. Read `.claude/skills/t27-wave-loop.md`.
+15. Update it with any new W774 pattern (if any; expected: same pattern as W773, no new compiler behaviour).
+16. Save one-line memory pointer in `MEMORY.md` via `/experience-save`.
+
+## 4. Cooperation variants for next Wave Loop
+
+- **Variant A (recommended):** continue odd outer-dimension ladder with `[369][2]^6 Pt` (~0.721 MiBit, 23,616 elements, 755,712-bit packed vector). Zero compiler changes expected.
+- **Variant B:** keep `[367][2]^6 Pt` width but move the packed var to bench/function scope to exercise function-local non-power-of-two packed arrays.
+- **Variant C:** add conditional (`if`) guarded indexed signed field writes at current `[367][2]^6 Pt` width to exercise control-flow + packed-vector writes.
+
+## 5. Exit criteria
+
+- W774 witness parses, lowers, simulates, cocotb-matches, and seals.
+- All cargo suites green.
+- Closeout report written and committed with `Closes #<ISSUE>`.
+- `.trinity/experience.md` updated.
+- Skills file updated and memory pointer saved.
+- Worktree clean of stale W485 artefacts.

.claude/plans/wave-loop-776.md

@@ -0,0 +1,51 @@
+# Wave Loop 776 Plan — Issue TBD
+
+## Phase 1: Issue
+- Confirm W776 issue (GitHub will assign next available number after #1485) and branch `wave-loop-776`.
+- Base branch: if PR #1484 (W774) and PR #1486 (W775) have both merged, branch from `master`; otherwise stack from `wave-loop-775` HEAD to keep the ladder unblocked.
+
+## Phase 2: Spec
+- Generate `specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27` using
+  `scripts/gen_w776.py` derived from `scripts/gen_w775.py`.
+- Constants: `OUTER = 371`, `TOTAL = 23744`, `LAST_IDX = 370`, `MID_IDX = 185`.
+
+## Phase 3: TDD
+- Inspect generated assertions: `make_grid(32768)`, `make_grid(1)`,
+  `call_write_grid`, field writes, `assert_eq` read-backs, mid and last checks.
+- Expected frame-condition element: `[185][1][0][0][0][0][0]` = element `185*64 + 32 = 11,872`.
+
+## Phase 4: Impl
+- Add integration test `accepts_w776_bench_module_371x2p6_aos_var_call_write` to
+  `bootstrap/tests/icarus_lowerable.rs` after the W775 test.
+- Zero compiler / reference-model / FROZEN_HASH changes expected.
+
+## Phase 5: Gen
+- Run `cd bootstrap && cargo build --release -p t27c`.
+
+## Phase 6: Seal
+- Run `./target/release/t27c seal --save specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27`.
+- Confirm FROZEN_HASH unchanged.
+
+## Phase 7: Verify
+- `./target/release/t27c parse specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27`
+- `./target/release/t27c icarus-lowerable specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27`
+- `./target/release/t27c icarus-simulate specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27` (17 cycles expected)
+- `./target/release/t27c icarus-cocotb specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27`
+- `cargo test -p t27c --bin t27c` (expected 1494/0/2)
+- `cargo test -p tri` (expected 78/0)
+- `cargo test -p t27c --test icarus_lowerable` (expected 236/0)
+
+## Phase 8: Land
+- Commit with `feat(igla): Wave Loop 776 — module-scope [371][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #<ISSUE>)`.
+- Push `wave-loop-776`, open PR #<ISSUE+1>, merge to `master` (or rebase/stack after W774/W775 land).
+
+## Phase 9: Learn
+- Write `docs/reports/FPGA_LOOP_CLOSEOUT_W776_2026-07-24.md`.
+- Save `.trinity/experience.md`, memory file, `MEMORY.md` pointer, and update
+  `.claude/skills/t27-wave-loop.md`.
+
+## Cooperation variants for next Wave Loop
+
+- **A (recommended):** `[373][2]^6 Pt` (~0.725 MiBit), continuing the odd ladder.
+- **B:** move the packed variable to bench/function scope at the current `[371][2]^6 Pt` width.
+- **C:** add conditional (`if`) indexed writes at the current `[371][2]^6 Pt` width.

.claude/skills/t27-wave-loop.md

@@ -709,4 +709,70 @@ expression → packed vector.
 
 ---
 
+## Worked example — Wave Loop 775
+
+Wave Loop 775 extended the odd outer-dimension ladder to `[369][2]^6 Pt` with no
+compiler changes, branching from `wave-loop-774` HEAD because PR #1484 (W774)
+remained open awaiting review:
+
+- Generated `scripts/gen_w775.py` from `scripts/gen_w774.py` with `OUTER = 369`
+  and `MID_IDX = 184`.
+- Produced `specs/scratch/w775_bench_module_369x2p6_aos_var_call_write.t27`
+  (23,616 elements, 755,712-bit packed vector, ~0.721 MiBit).
+- Added integration test `accepts_w775_bench_module_369x2p6_aos_var_call_write`
+  after the existing W775 tests in `bootstrap/tests/icarus_lowerable.rs`.
+- Ran `t27c parse`, `icarus-lowerable`, `icarus-simulate` (17 cycles, PASSED),
+  `icarus-cocotb` (reference-model OK), and `t27c seal --save`.
+- No changes to `bootstrap/src/compiler.rs`, `bootstrap/stage0/FROZEN_HASH`, or
+  `scripts/cocotb_ref_model.py`.
+- Validation: `cargo build --release -p t27c` green,
+  `cargo test -p t27c --bin t27c` 1494/0/2, `cargo test -p tri` 78/0,
+  `cargo test -p t27c --test icarus_lowerable` 235/0,
+  `./scripts/tri test --icarus-lowerable --icarus-simulate --cocotb` 53/0 Icarus
+  PASS, 53/0 cocotb PASS, 0 seal mismatches.
+- Refreshed weak-point audit and 2025-2026 ternary/MVL literature scan.
+- Wrote `docs/reports/FPGA_LOOP_CLOSEOUT_W775_2026-07-24.md` and proposed three
+  cooperation variants for W776: `[371][2]^6 Pt` (recommended), bench/function
+  scope at `[369][2]^6 Pt`, and `if`-guarded writes at `[369][2]^6 Pt`.
+
+Key learning: when the previous wave's PR is still open, branch the next wave
+from the previous wave branch HEAD so the sequence can continue. Maintain the
+same mechanical generator discipline, and keep the `make_grid(32768)`
+period-identity check because `32768 ≡ 0 (mod 32768)`. Keep using `assert_eq` on
+changed elements because `assert_ne` is not emitted by the Icarus simulation
+path.
+
+## Worked example — Wave Loop 774
+
+Wave Loop 774 exercised the odd outer-dimension ladder with no compiler changes,
+confirming that the existing packed-vector lowering scales to `[367][2]^6 Pt`:
+
+- Generated `scripts/gen_w774.py` from `scripts/gen_w773.py` with `OUTER = 367`
+  and `MID_IDX = 183`.
+- Produced `specs/scratch/w774_bench_module_367x2p6_aos_var_call_write.t27`
+  (23,488 elements, 751,616-bit packed vector, ~0.717 MiBit).
+- Added integration test `accepts_w774_bench_module_367x2p6_aos_var_call_write` in
+  `bootstrap/tests/icarus_lowerable.rs`.
+- Ran `t27c parse`, `icarus-lowerable`, `icarus-simulate` (17 cycles, PASSED),
+  `icarus-cocotb` (reference-model OK), and `t27c seal --save`.
+- No changes to `bootstrap/src/compiler.rs`, `bootstrap/stage0/FROZEN_HASH`, or
+  `scripts/cocotb_ref_model.py`.
+- Validation: `cargo build --release -p t27c` green,
+  `cargo test -p t27c --bin t27c` 1494/0/2, `cargo test -p tri` 78/0,
+  `cargo test -p t27c --test icarus_lowerable` 234/0.
+- Wrote `docs/reports/FPGA_LOOP_CLOSEOUT_W774_2026-07-24.md` and proposed three
+  cooperation variants for W775: `[369][2]^6 Pt` (recommended), bench/function
+  scope at `[367][2]^6 Pt`, and `if`-guarded writes at `[367][2]^6 Pt`.
+
+Key learning: when a wave is purely a width/scaling regression, the safest
+implementation is a mechanical copy of the previous generator with only the
+outer-dimension and mid-index constants changed. Always keep the `make_grid(32768)`
+period-identity check because `32768 ≡ 0 (mod 32768)`, and use `assert_eq` on
+changed elements since `assert_ne` is not emitted by the Icarus simulation path.
+Also use the /loop iteration to refresh the weak-point audit and literature
+scan even when no compiler code changes, so closeout reports remain honest about
+traceability drift and worktree hygiene.
+
+---
+
 *φ² + φ⁻² = 3 | TRINITY*

.trinity/current-issue.md

@@ -1,45 +1,52 @@
-# Wave Loop 773 — Issue #1481
+# Wave Loop 775 — Issue TBD
 
-**Branch:** `wave-loop-773`  
+**Branch:** `wave-loop-775`  
+**Parent branch:** `wave-loop-774` HEAD (`433102763`)  
 **Date:** 2026-07-24  
-**Cooperation variant:** A (recommended)
+**Issue:** #1485  
+**PR:** #1486 (TBD)  
+**Cooperation variant:** A (recommended)  
+**Status:** implementation complete, pending PR review and merge
 
 ## Goal
 
-Close Wave Loop 773 by validating a module-scope `[365][2]^6 Pt` packed
+Close Wave Loop 775 by validating a module-scope `[369][2]^6 Pt` packed
 array-of-struct variable initialized from a function call, with indexed signed
-field writes and `assert_eq` read-back in a `bench` block.
+field writes and `assert_eq` read-back in a `bench` block. W774 PR #1484 is
+still open awaiting review, so W775 was branched from `wave-loop-774` HEAD
+to avoid blocking the sequence.
 
 ## Acceptance criteria
 
-1. `specs/scratch/w773_bench_module_365x2p6_aos_var_call_write.t27` is generated and parses.
-2. The witness is Icarus-lowerable and simulates correctly (17 cycles, PASSED).
-3. The cocotb reference model matches the t27 semantics.
-4. `t27c seal --save` succeeds and FROZEN_HASH remains unchanged.
-5. All cargo suites remain green.
-6. Integration test `accepts_w773_bench_module_365x2p6_aos_var_call_write` is added.
-7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W773_2026-07-24.md` is written.
-8. Learning is saved to `.trinity/experience.md`, memory, and `skills-wave-loop-recipe.md`.
-9. Branch merges to `master` with `Closes #1481`.
+1. [x] `specs/scratch/w775_bench_module_369x2p6_aos_var_call_write.t27` is generated and parses.
+2. [x] The witness is Icarus-lowerable and simulates correctly (17 cycles, PASSED).
+3. [x] The cocotb reference model matches the t27 semantics.
+4. [x] `t27c seal --save` succeeds and FROZEN_HASH remains unchanged.
+5. [x] All cargo suites remain green.
+6. [x] Integration test `accepts_w775_bench_module_369x2p6_aos_var_call_write` is added.
+7. [x] Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W775_2026-07-24.md` is written.
+8. [x] Learning is saved to `.trinity/experience.md`, memory, `.claude/skills/t27-wave-loop.md`, and `.trinity/current-issue.md`.
+9. [ ] GitHub issue for W775 is created and PR #<issue+1> opened with `Closes #<issue>`.
+10. [ ] PR #<issue+1> reviewed and merged to `master` (or stacked after W774 lands).
 
 ## Technical notes
 
-- Shape: `[365][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
-- Total elements: `365 x 64 = 23,360`.
-- Packed vector width: `23,360 x 32 = 747,520` bits (~0.713 MiBit).
-- `MID_IDX = 182`; frame-condition element `[182][1][0][0][0][0][0]` is element
-  `182*64 + 32 = 11,680`.
-- Generator script: `scripts/gen_w773.py` (copy from `scripts/gen_w772.py`, set
-  `OUTER = 365` and `MID_IDX = 182`, manually fix the f-string header).
+- Shape: `[369][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
+- Total elements: `369 x 64 = 23,616`.
+- Packed vector width: `23,616 x 32 = 755,712` bits (~0.721 MiBit).
+- `MID_IDX = 184`; frame-condition element `[184][1][0][0][0][0][0]` is element
+  `184*64 + 32 = 11,808`.
+- Generator script: `scripts/gen_w775.py` (copy from `scripts/gen_w774.py`, set
+  `OUTER = 369` and `MID_IDX = 184`, manually fix the f-string header).
 - Use `assert_eq` checks on changed elements (Icarus simulation path does not
   emit `assert_ne`).
 - Include `make_grid(32768)` period-identity check because `32768 == 0 (mod 32768)`.
 - Zero compiler / reference-model / FROZEN_HASH changes expected.
 
 ## Cooperation variants for next Wave Loop
 
-- **Variant A (recommended):** continue the odd outer-dimension ladder with `[367][2]^6 Pt`.
-- **Variant B:** keep width at ~0.713 MiBit but move the packed var to bench/function scope.
+- **Variant A (recommended):** continue the odd outer-dimension ladder with `[371][2]^6 Pt`.
+- **Variant B:** keep width at ~0.721 MiBit but move the packed var to bench/function scope.
 - **Variant C:** add `if`-guarded indexed signed field writes at the current width.
 
 ---

.trinity/current_task/activity.md

@@ -3732,3 +3732,19 @@
 - **Commit:** docs(trinity): Wave Loop 773 closeout report, experience, and updated plan
 - **Files:** .claude/plans/wave-loop-774.md,docs/NOW.md
 
+## 2026-07-23T19:34:18Z — wave-loop-774
+- **Commit:** docs(trinity): update NOW.md for W773 close-out / W774 setup and add wave-loop-774 plan
+- **Files:** .trinity/current-issue.md
+
+## 2026-07-24T11:09:43Z — wave-loop-774
+- **Commit:** docs(trinity): Wave Loop 774 branch setup and cooperation variants
+- **Files:** .claude/plans/loop-w774-full-cycle.md,.claude/skills/t27-wave-loop.md,.trinity/current-issue.md,.trinity/experience.md,.trinity/seals/scratch_w774_bench_module_367x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/reports/FPGA_LOOP_CLOSEOUT_W774_2026-07-24.md,scripts/gen_w774.py,specs/scratch/w774_bench_module_367x2p6_aos_var_call_write.t27
+
+## 2026-07-24T11:10:22Z — wave-loop-774
+- **Commit:** feat(igla): Wave Loop 774 — module-scope [367][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1483)
+- **Files:** .trinity/current-issue.md
+
+## 2026-07-24T12:17:16Z — wave-loop-775
+- **Commit:** docs(trinity): update current-issue.md with PR #1484 link for Wave Loop 774 (Refs #1483)
+- **Files:** .claude/plans/wave-loop-776.md,.claude/skills/t27-wave-loop.md,.trinity/current-issue.md,.trinity/experience.md,.trinity/seals/scratch_w775_bench_module_369x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/reports/FPGA_LOOP_CLOSEOUT_W775_2026-07-24.md,scripts/gen_w775.py,specs/scratch/w775_bench_module_369x2p6_aos_var_call_write.t27
+