Wave Loop 785: module-scope [389][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable

.claude/plans/loop-w774-full-cycle.md

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+# /loop Iteration Plan — W774 Closeout + Audit + Literature + Skills
+
+**Date:** 2026-07-24  
+**Branch:** `wave-loop-774`  
+**Issue:** TBD (next available GitHub issue)  
+**Anchor:** φ² + φ⁻² = 3 | TRINITY
+
+## 0. Prompt from user
+
+> 15m loop: исследуй слабые места работы, исследуй научные работы по теме, создай декомпозированный план и реализуй все и в конце отчет и три варианта сотрудничества для следующего Wave лупа! сохрани в конце скилы.
+
+## 1. Weak-point audit (done in this iteration)
+
+| Metric | Current | Previous (W773) | Verdict |
+|--------|---------|-----------------|---------|
+| 30-day commits | 66 | — | — |
+| Subject-line `Closes #N` / `Fixes #N` | 10 / 66 ≈ 15.2% | ~84% | **REGRESSION** — many merge/closeout commits carry link only in body |
+| `.t27` specs without `test`/`invariant`/`bench` | 51 / 880 ≈ 5.8% | ~6.5% | **IMPROVED** |
+| `scripts/*.sh` on critical path | 19 | 19 | **STABLE** |
+| Untracked worktree noise | `specs/scratch/w485_*.t27` × 3 + `wave-loop-485.md` | — | **WEAK POINT** — stale W485 artefacts |
+| Pre-existing FPGA/formal CI failures | `sby` missing, Yosys Verilog-2005 static-cast in `build/fpga/generated/uart.v` | same | tracked as #1245, unrelated |
+
+**Top weak points to address during this cycle:**
+1. **L1 traceability drift:** 30-day subject-line issue-link rate dropped from ~84% to ~15%. Continue putting `Closes #<ISSUE>` in subject lines for feat/merge/closeout commits.
+2. **Stale W485 artefacts:** untracked `specs/scratch/w485_*.t27` and `.claude/plans/wave-loop-485.md` should be either committed or removed before W774 closeout.
+3. **NOW.md staleness:** `NOW.md` last updated 2026-05-24 and does not reflect current wave-loop work.
+
+## 2. Literature scan (done in this iteration)
+
+### Ternary / MVL EDA (2025–2026)
+- **SONIC** — event-driven gate-level simulator/verifier for ternary VLSI using delta cycles, BCT Verilog FPGA export (IEEE ISMVL 2026) [doi:10.1109/ismvl68998.2026.00042](https://doi.org/10.1109/ismvl68998.2026.00042).
+- **TVHDL** — balanced-ternary extension to IEEE 1076-2008 VHDL, verified with GHDL/GTKWave (IEEE ISMVL 2026) [doi:10.1109/ismvl68998.2026.00041](https://doi.org/10.1109/ismvl68998.2026.00041).
+- **KULeuven ternary-lut-dse** — Chisel generator for LUT-based ternary MatMul targeting 1.58-bit LLMs, accepted IEEE ISPASS 2026 ([GitHub](https://github.com/KULeuven-MICAS/ternary-lut-dse)).
+- **TerEffic** — ternary LLM inference on AMD Alveo U280 with LUT-based TMat Core, arXiv 2025 ([arXiv:2502.16473](https://arxiv.org/html/2502.16473v2)).
+
+### Verification / cocotb (2025–2026)
+- **DVCon EU 2025** — unified FPGA firmware verification with cocotb + pytest + shared scoreboard/Python reference model ([paper PDF](https://dvcon-proceedings.org/wp-content/uploads/DVConEU_2025_paper_95.pdf)).
+- **cocotb 2.0/2.1** — `@cocotb.parametrize`, `cocotb_tools.runner.Runner`, pytest integration, JUnit XML improvements ([release notes](https://docs.cocotb.org/en/development/release_notes.html)).
+
+### Relevance to t27
+- t27’s scalar packed-vector lowering avoids native Icarus/Yosys gaps with arrays of packed structs, consistent with literature trend of flattening to wide vectors.
+- cocotb 2.x pytest convergence supports the existing `t27c icarus-cocotb` reference-model path.
+
+## 3. Decomposed implementation plan
+
+### Phase A — Housekeeping (15 min)
+1. Decide fate of stale W485 artefacts:
+   - Option 1: delete untracked `specs/scratch/w485_*.t27` and `wave-loop-485.md` if W485 is abandoned.
+   - Option 2: open issue #1455, branch `wave-loop-485`, and stage them.
+   - **Recommendation:** delete from this branch; W485 can be recreated from the plan file in git history if needed.
+2. Update `.trinity/current-issue.md` with actual GitHub issue number once known.
+
+### Phase B — W774 Spec + Test (30 min)
+3. Generate `scripts/gen_w774.py` from `scripts/gen_w773.py` with `OUTER = 367`, `MID_IDX = 183`.
+4. Run generator to produce `specs/scratch/w774_bench_module_367x2p6_aos_var_call_write.t27`.
+5. Manually fix the f-string module header (`{OUTER}` → actual number) if generator emits it literally.
+6. Add integration test `accepts_w774_bench_module_367x2p6_aos_var_call_write` to `bootstrap/tests/icarus_lowerable.rs`.
+
+### Phase C — Build + Seal + Verify (45 min)
+7. `cd bootstrap && cargo build --release -p t27c`.
+8. `t27c parse`, `icarus-lowerable`, `icarus-simulate` (17 cycles), `icarus-cocotb` on the W774 witness.
+9. `t27c seal --save` the witness; confirm `FROZEN_HASH` unchanged.
+10. `cargo test -p t27c --bin t27c`, `cargo test -p tri`, `cargo test -p t27c --test icarus_lowerable`.
+
+### Phase D — Closeout + Cooperation Variants (30 min)
+11. Write `docs/reports/FPGA_LOOP_CLOSEOUT_W774_2026-07-24.md` with:
+    - what worked, what changed behavior, validation matrix, scientific background, weak-point audit, literature scan.
+12. Append W774 learnings to `.trinity/experience.md`.
+13. Propose three cooperation variants for W775 in the closeout report and in `.trinity/current-issue.md`.
+
+### Phase E — Save Skills (15 min)
+14. Read `.claude/skills/t27-wave-loop.md`.
+15. Update it with any new W774 pattern (if any; expected: same pattern as W773, no new compiler behaviour).
+16. Save one-line memory pointer in `MEMORY.md` via `/experience-save`.
+
+## 4. Cooperation variants for next Wave Loop
+
+- **Variant A (recommended):** continue odd outer-dimension ladder with `[369][2]^6 Pt` (~0.721 MiBit, 23,616 elements, 755,712-bit packed vector). Zero compiler changes expected.
+- **Variant B:** keep `[367][2]^6 Pt` width but move the packed var to bench/function scope to exercise function-local non-power-of-two packed arrays.
+- **Variant C:** add conditional (`if`) guarded indexed signed field writes at current `[367][2]^6 Pt` width to exercise control-flow + packed-vector writes.
+
+## 5. Exit criteria
+
+- W774 witness parses, lowers, simulates, cocotb-matches, and seals.
+- All cargo suites green.
+- Closeout report written and committed with `Closes #<ISSUE>`.
+- `.trinity/experience.md` updated.
+- Skills file updated and memory pointer saved.
+- Worktree clean of stale W485 artefacts.

.claude/plans/loop-w776-full-cycle.md

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+# Wave Loop 776 — Full-cycle decomposed plan
+
+## Charter
+Investigate repository weak points, research scientific literature, create a
+decomposed plan, implement Wave Loop 776, write a closeout report with three
+cooperation variants for Wave Loop 777, and save skills / experience.
+
+## 1. Weak-point audit
+- [x] Branch / worktree hygiene: `wave-loop-775` is current; W774 PR #1484 and
+  W775 PR #1486 are open awaiting review, so W776 will branch from
+  `wave-loop-775` HEAD to avoid blocking.
+- [x] Traceability: 13 of 69 recent 30-day commit subjects carry
+  `Closes #N`/`Fixes #N`/`Refs #N` (~18.8%). Subjects remain low, but
+  closeout bodies still contain issue links.
+- [x] Testability: 57 of 882 `.t27` specs lack `test`/`invariant`/`bench`
+  (~6.5%). This is within the historical band but should be tracked.
+- [x] UNITY: 19 `*.sh` scripts remain under `scripts/`. No new shell scripts
+  will be added on the W776 critical path.
+- [x] Worktree needles: untracked W485 scratch artifacts
+  (`w485_bench_local_array_hoist.t27`, `w485_host_helper_shadow.t27`,
+  `w485_wildcard_binding.t27`) and stale `.claude/plans/w485*` remain
+  uncommitted and unrelated to the wave ladder.
+- [x] CI weak points: pre-existing Yosys/Icarus FPGA synthesis formal failures
+  (`sby` pip package missing, Yosys static-cast Verilog-2005 limitation in
+  `build/fpga/generated/uart.v`) are unchanged and out of scope for this wave.
+
+## 2. Literature scan (2025-2026)
+- SystemVerilog packed array / struct semantics: IEEE 1800-2017 7.4.1/7.4.3
+  confirm packed width is the product of dimensions, with no power-of-two
+  restriction. AMD UG901 2026.1 lists packed arrays and packed structs as
+  supported in Vivado synthesis/simulation.
+- Tool gaps: Yosys 0.65-dev docs still note that arrays of packed structs/unions
+  are not supported (YosysHQ/yosys#2677, #2908, #5837). t27's scalar
+  packed-vector flattening avoids the unsupported construct entirely.
+- Ternary/MVL ecosystem (IEEE ISMVL 2025/2026):
+  - REBEL-6 — 32-trit balanced ternary ISA with RV32I-to-REBEL C compiler.
+  - SONIC — event-driven gate-level ternary VLSI simulator with delta cycles.
+  - TVHDL — balanced ternary extension to IEEE 1076-2008 VHDL.
+  - VTX1 — open-source balanced-ternary SoC with Icarus/Yosys RTL-to-silicon flow.
+
+## 3. Implementation plan
+- Create `wave-loop-776` from `wave-loop-775` HEAD.
+- Copy `scripts/gen_w775.py` to `scripts/gen_w776.py`.
+- Update constants: `OUTER = 371`, `MID_IDX = 185`.
+- Update module name prefix to `w776_bench_module_371x2p6_aos_var_call_write`.
+- Run generator to produce
+  `specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27`.
+- Add integration test `accepts_w776_bench_module_371x2p6_aos_var_call_write`
+  in `bootstrap/tests/icarus_lowerable.rs` after the W775 test.
+- Build `cargo build --release -p t27c`.
+- Seal the witness with `t27c seal --save`.
+- Verify: `parse`, `icarus-lowerable`, `icarus-simulate` (17 cycles),
+  `icarus-cocotb`.
+- Run cargo suites: `cargo test -p t27c --bin t27c`, `cargo test -p tri`,
+  `cargo test -p t27c --test icarus_lowerable`.
+- Create GitHub issue for W776.
+- Commit with `Closes #<issue>`.
+- Push `wave-loop-776` and open PR.
+
+## 4. Closeout / learning
+- Write `docs/reports/FPGA_LOOP_CLOSEOUT_W776_2026-07-24.md`.
+- Write `.claude/plans/wave-loop-777.md` with three cooperation variants.
+- Update `.trinity/experience.md`, `.claude/skills/t27-wave-loop.md`,
+  `.trinity/current-issue.md`, and `docs/NOW.md`.
+- Save memory file `wave-loop-776.md` and prepend pointer in `MEMORY.md`.
+
+## 5. Cooperation variants for Wave Loop 777
+- **Variant A (recommended):** continue the odd outer-dimension ladder with
+  `[373][2]^6 Pt` (~0.725 MiBit).
+- **Variant B:** keep width at ~0.723 MiBit but move the packed var to
+  bench/function scope at `[371][2]^6 Pt`.
+- **Variant C:** add `if`-guarded indexed signed field writes at the current
+  `[371][2]^6 Pt` width.

.claude/plans/loop-w777-full-cycle.md

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+# Wave Loop 777 — Full-cycle plan (PHI LOOP)
+
+**Date:** 2026-07-24  
+**Issue:** #1490 (next available after #1487/#1488/#1489)  
+**Branch:** `wave-loop-777`  
+**Base:** `wave-loop-776` HEAD (`484c41725`) because PR #1484/W774, #1486/W775, #1488/W776, and #1489/README-merge are still open/unstable.
+
+---
+
+## Phase 1: Issue
+
+- Create GitHub issue #1490: *Wave Loop 777 — module-scope `[373][2]^6 Pt` non-power-of-two packed array-of-struct variable from call with indexed signed writes*.
+- Label: none (the `wave-loop` label does not exist in this repo; proven by prior loops).
+- Branch `wave-loop-777` from `wave-loop-776` HEAD.
+
+## Phase 2: Spec
+
+- Copy `scripts/gen_w776.py` → `scripts/gen_w777.py`.
+- Set `OUTER = 373`, `MID_IDX = 186`.
+- Fix module prefix `w776` → `w777` in the header string.
+- Run generator to produce `specs/scratch/w777_bench_module_373x2p6_aos_var_call_write.t27`.
+- Shape: `[373][2]^6 Pt` = `373 × 64 = 23,872` elements, packed vector `23,872 × 32 = 764,416` bits (~0.729 MiBit).
+- Frame-condition element: `[186][1][0][0][0][0][0]` = element `186 × 64 + 32 = 11,936`.
+
+## Phase 3: TDD
+
+- Inspect generated file:
+  - `pub var dst : [373][2]^6 Pt = make_grid(0);`
+  - `make_grid(32768)` period-identity check present.
+  - `assert_eq` read-back in `bench` block (not `assert_ne`, because Icarus path does not emit it).
+  - Multi-line brace style preserved.
+- Verify expected values manually:
+  - `LAST_IDX = 372`
+  - `LAST_E = 372 × 64 + 63 = 23,871`
+  - `LAST_X = (2 × 23871) % 32768 = 47742 % 32768 = 14974`
+  - `LAST_Y = 14975`
+  - `MID_E = 186 × 64 + 32 = 11,936`
+  - `MID_X = (2 × 11936) % 32768 = 23872 % 32768 = 23872`
+  - `MID_Y = 23873`
+  - `WRAP_LAST_X = (2 × 23871 + 32768) % 32768 = 14974` (same as LAST_X because +32768 ≡ 0)
+
+## Phase 4: Impl
+
+- Add integration test `accepts_w777_bench_module_373x2p6_aos_var_call_write` to `bootstrap/tests/icarus_lowerable.rs` after W776 test.
+- Zero changes to `bootstrap/src/compiler.rs`, `scripts/cocotb_ref_model.py`, or `bootstrap/stage0/FROZEN_HASH`.
+
+## Phase 5: Gen
+
+- `cargo build --release -p t27c`.
+
+## Phase 6: Seal
+
+- `./target/release/t27c seal --save specs/scratch/w777_bench_module_373x2p6_aos_var_call_write.t27`.
+- Confirm `bootstrap/stage0/FROZEN_HASH` unchanged: `68a0b933c00ba5efd7facb5997f00880c3eecae55e6ac5e8cea2aee399b92adc`.
+
+## Phase 7: Verify
+
+- `./target/release/t27c parse specs/scratch/w777_bench_module_373x2p6_aos_var_call_write.t27`
+- `./target/release/t27c icarus-lowerable specs/scratch/w777_bench_module_373x2p6_aos_var_call_write.t27`
+- `./target/release/t27c icarus-simulate specs/scratch/w777_bench_module_373x2p6_aos_var_call_write.t27` (17 cycles expected)
+- `./target/release/t27c icarus-cocotb specs/scratch/w777_bench_module_373x2p6_aos_var_call_write.t27`
+- `cargo test -p t27c --bin t27c` → 1494/0/2
+- `cargo test -p tri` → 78/0
+- `cargo test -p t27c --test icarus_lowerable` → 237/0
+
+## Phase 8: Land
+
+- Commit: `feat(igla): Wave Loop 777 — module-scope [373][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1490)`.
+- Push `wave-loop-777`.
+- Open PR #1491.
+- Do **not** force-merge; previous merge attempts showed branch-protection rules and required checks block admin merges when checks fail. Record the blocker honestly.
+
+## Phase 9: Learn
+
+- Write `docs/reports/FPGA_LOOP_CLOSEOUT_W777_2026-07-24.md` with:
+  - summary,
+  - verification matrix,
+  - weak-point audit (inherited and newly discovered),
+  - 2024–2025 literature scan,
+  - three cooperation variants for Wave Loop 778.
+- Save `.trinity/experience.md`, memory file, `MEMORY.md` index, `.claude/skills/t27-wave-loop.md`, and `.trinity/current-issue.md`.
+
+---
+
+## Cooperation variants for Wave Loop 778
+
+| Variant | Scope | Outer dim | Packed bits | Risk | Recommendation |
+|:--------|:------|----------:|------------:|:-----|:---------------|
+| **A (recommended)** | module-scope var | 375 | 768,000 (~0.733 MiBit) | low | continues odd-integer ladder; mechanical generator change only |
+| **B** | bench/function-scope var | 373 | 764,416 (~0.729 MiBit) | medium | tests lowering of non-module packed arrays, may hit scoping rules |
+| **C** | conditional indexed writes | 373 | 764,416 (~0.729 MiBit) | medium | adds `if`-guarded signed field writes; tests control-flow + memory interaction |
+
+---
+
+## Weak-point audit (pre-W777)
+
+1. **CI: `fpga-synthesis` fails on `uart.v` static cast** — inherited, blocks PR #1489. Error: `Static cast is only supported in SystemVerilog mode` at `build/fpga/generated/uart.v:31`. Wave-loop witnesses are not in the synthesis target, so they do not cause this.
+2. **Test drift: `sequencer_idle_arms_on_start`** — `bootstrap/tests/bitnet_pipeline.rs:143` expects exact string `IDLE: if(start) begin ...` but actual output now wraps it with `IDLE: begin done<=0; if(start) begin ... end end`. Pre-existing failure in `cargo test -p t27c` (bitnet_pipeline test).
+3. **Branch-protection friction:** direct `master` push forbidden; `--admin` merge rejected while required checks are red. The honest path is to fix the red checks or merge via GitHub web UI with admin override.
+4. **`main` vs `master` divergence:** a separate `main` branch exists with useful work (dlc10, Verilog struct access, TRI-NET) but dozens of add/add conflicts against `master`; needs dedicated merge session.
+5. **Traceability drift recovered locally:** last-30-day commit subjects with `Closes #`/`Fixes #` are ~80% (57/71) in current activity, but the overall 30-day remote rate remains lower; keep monitoring.
+
+---
+
+## 2024–2025 literature scan (relevant to W777)
+
+- **TerEffic** (arXiv 2025) — packs 5 ternary weights into 8 bits because 3⁵ = 243 < 256, directly relevant to non-power-of-two packed ternary arrays: https://arxiv.org/html/2502.16473v2
+- **TENET** (arXiv 2025) — LUT-centric ternary LLM accelerator with 64-byte → 80-byte weight decompression (1.6 bits/weight): https://arxiv.org/html/2509.13765
+- **KULeuven-MICAS/ternary-lut-dse** (GitHub, IEEE ISPASS 2026) — Chisel generator for LUT-based ternary matrix multiplication with non-power-of-two LUT depths `(3^µ - 1)/2`: https://github.com/KULeuven-MICAS/ternary-lut-dse
+- **Generalized Multiple-Valued FPGA Architecture** (IEEE Access 2025) — T-gate based MVL FPGA CLB merging LUT and FF: https://doi.org/10.1109/access.2025.3605842
+- **VTX1** (GitHub 2025) — balanced-ternary SoC in Icarus Verilog: https://github.com/itworks99/vtx1
+- **TernaryCore** (GitHub 2025) — native `{-1,0,+1}` BitNet accelerator in Verilog: https://github.com/shepherdscientific/ternarycore
+
+All sources listed above will be cited in the closeout report.
+
+---
+
+φ² + 1/φ² = 3 | TRINITY

.claude/plans/wave-loop-776.md

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+# Wave Loop 776 Plan — Issue TBD
+
+## Phase 1: Issue
+- Confirm W776 issue (GitHub will assign next available number after #1485) and branch `wave-loop-776`.
+- Base branch: if PR #1484 (W774) and PR #1486 (W775) have both merged, branch from `master`; otherwise stack from `wave-loop-775` HEAD to keep the ladder unblocked.
+
+## Phase 2: Spec
+- Generate `specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27` using
+  `scripts/gen_w776.py` derived from `scripts/gen_w775.py`.
+- Constants: `OUTER = 371`, `TOTAL = 23744`, `LAST_IDX = 370`, `MID_IDX = 185`.
+
+## Phase 3: TDD
+- Inspect generated assertions: `make_grid(32768)`, `make_grid(1)`,
+  `call_write_grid`, field writes, `assert_eq` read-backs, mid and last checks.
+- Expected frame-condition element: `[185][1][0][0][0][0][0]` = element `185*64 + 32 = 11,872`.
+
+## Phase 4: Impl
+- Add integration test `accepts_w776_bench_module_371x2p6_aos_var_call_write` to
+  `bootstrap/tests/icarus_lowerable.rs` after the W775 test.
+- Zero compiler / reference-model / FROZEN_HASH changes expected.
+
+## Phase 5: Gen
+- Run `cd bootstrap && cargo build --release -p t27c`.
+
+## Phase 6: Seal
+- Run `./target/release/t27c seal --save specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27`.
+- Confirm FROZEN_HASH unchanged.
+
+## Phase 7: Verify
+- `./target/release/t27c parse specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27`
+- `./target/release/t27c icarus-lowerable specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27`
+- `./target/release/t27c icarus-simulate specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27` (17 cycles expected)
+- `./target/release/t27c icarus-cocotb specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27`
+- `cargo test -p t27c --bin t27c` (expected 1494/0/2)
+- `cargo test -p tri` (expected 78/0)
+- `cargo test -p t27c --test icarus_lowerable` (expected 236/0)
+
+## Phase 8: Land
+- Commit with `feat(igla): Wave Loop 776 — module-scope [371][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #<ISSUE>)`.
+- Push `wave-loop-776`, open PR #<ISSUE+1>, merge to `master` (or rebase/stack after W774/W775 land).
+
+## Phase 9: Learn
+- Write `docs/reports/FPGA_LOOP_CLOSEOUT_W776_2026-07-24.md`.
+- Save `.trinity/experience.md`, memory file, `MEMORY.md` pointer, and update
+  `.claude/skills/t27-wave-loop.md`.
+
+## Cooperation variants for next Wave Loop
+
+- **A (recommended):** `[373][2]^6 Pt` (~0.725 MiBit), continuing the odd ladder.
+- **B:** move the packed variable to bench/function scope at the current `[371][2]^6 Pt` width.
+- **C:** add conditional (`if`) indexed writes at the current `[371][2]^6 Pt` width.