feat(igla): Wave Loop 420 — VCD exact-terminator + auto-threshold, PVT process-corner monotonicity#1362
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…shold, PVT process-corner monotonicity Closes #1361 Variant C fallback (bench still blocked: P12 unwired, DLC10 cable missing, no relay). Instrument-import depth and formal guarding only. - cli/tri/src/fpga.rs: - exact-token VCD $date/$version/$comment terminator with regression test for embedded $end-like tokens (closes W419 report/actual gap) - real-valued VCD net auto-threshold from observed voltage swing - PVT half-period process-corner monotonicity regression test - proofs/lean4/Trinity/TernaryFPGABoot.lean: - pvt_half_ns_monotone_in_process_corner (ff ≤ tt ≤ ss) - fpga/HARDWARE_SSOT.md: §3.6.17 documenting W420 VCD/PVT improvements - .trinity/experience.md: W420 learnings - docs/reports: W420 report, evidence, and W421 cooperation variants Verification: - cargo test -p tri vcd: 13/13 PASS - cargo test -p tri pvt: 10/10 PASS - cargo test -p tri fpga::tests: 48/48 PASS - lake build Trinity.TernaryFPGABoot: PASS (2967 jobs) - ./scripts/tri test: 16 pre-existing yosys failures (#1245), no new ones Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-07-04 19:30:46 UTC
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This was referenced Jul 4, 2026
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This was referenced Jul 6, 2026
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Closing: stale wave-loop-4xx PR, superseded by later waves. Reopen if still relevant. |
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PR DashboardGenerated at: 2026-07-06 15:01:39 UTC
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This was referenced Jul 6, 2026
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Wave Loop 420 closes #1361 (Variant C fallback — bench still blocked).\n\nSee full report: docs/reports/WAVE_LOOP_420_REPORT.md\nEvidence: docs/reports/FPGA_LOOP_EVIDENCE_W420_2026-07-06.md\nNext wave variants: docs/reports/FPGA_LOOP_COOPERATION_W421_2026-07-06.md\n\nCloses #1361\n\n🤖 Generated with Claude Code