feat(igla): Wave Loop 423 — CSV time units, VCD slope filter, PVT worst-case, competitor refresh#1372
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feat(igla): Wave Loop 423 — CSV time units, VCD slope filter, PVT worst-case, competitor refresh#1372gHashTag wants to merge 8 commits into
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…shold, PVT process-corner monotonicity Closes #1361 Variant C fallback (bench still blocked: P12 unwired, DLC10 cable missing, no relay). Instrument-import depth and formal guarding only. - cli/tri/src/fpga.rs: - exact-token VCD $date/$version/$comment terminator with regression test for embedded $end-like tokens (closes W419 report/actual gap) - real-valued VCD net auto-threshold from observed voltage swing - PVT half-period process-corner monotonicity regression test - proofs/lean4/Trinity/TernaryFPGABoot.lean: - pvt_half_ns_monotone_in_process_corner (ff ≤ tt ≤ ss) - fpga/HARDWARE_SSOT.md: §3.6.17 documenting W420 VCD/PVT improvements - .trinity/experience.md: W420 learnings - docs/reports: W420 report, evidence, and W421 cooperation variants Verification: - cargo test -p tri vcd: 13/13 PASS - cargo test -p tri pvt: 10/10 PASS - cargo test -p tri fpga::tests: 48/48 PASS - lake build Trinity.TernaryFPGABoot: PASS (2967 jobs) - ./scripts/tri test: 16 pre-existing yosys failures (#1245), no new ones Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Closes #1363 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
… PVT monotonicity, competitor snapshot Closes #1363 Variant C fallback (bench still blocked: openFPGALoader --detect reports 0 devices). - cli/tri/src/fpga.rs: - apply vcd_line_ends_with_token to $timescale terminator - add test_parse_vcd_timescale_with_embedded_end_token - add test_parse_vcd_real_auto_threshold_us_timescale - add test_pvt_half_ns_monotone_combined - proofs/lean4/Trinity/TernaryFPGABoot.lean: - add pvt_half_ns_monotone_combined - fpga/HARDWARE_SSOT.md: §3.6.18 documenting W421 improvements - docs/reports/T27_VS_FORMAL_HDL_2026.md: competitor comparison - .trinity/experience.md: W421 learnings - docs/reports: W421 report, evidence, and W422 cooperation variants Verification: - cargo test -p tri vcd: 15/15 PASS - cargo test -p tri pvt: 11/11 PASS - cargo test -p tri fpga::tests: 51/51 PASS - lake build Trinity.TernaryFPGABoot: PASS (2967 jobs) - ./scripts/tri test: 16 pre-existing yosys failures (#1245), no new ones Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…escape, PVT worst-case bound Closes #1365 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Closes #1368 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…st-case, competitor refresh (Closes #1368) - cli/tri/src/fpga.rs: CSV ms/us/ns/sample-number normalization, VCD real-net slope filter, unknown timescale fallback, dumpoff/dumpon without timestamp, --pvt-worstcase mode; +10 regression tests (60/60 PASS). - fpga/HARDWARE_SSOT.md: add §3.6.20 documenting W423 instrument-import depth. - docs/reports/T27_VS_FORMAL_HDL_2026.md: refresh Sparkle/Verilean, Clash, CIRCT. - docs/reports/WAVE_LOOP_423_REPORT.md, FPGA_LOOP_EVIDENCE_W423_2026-07-05.md, FPGA_LOOP_COOPERATION_W424_2026-07-05.md: W423 close-out + W424 variants. - docs/NOW.md, .trinity/experience.md, .trinity/current-issue.md: W423 close-out and W424 setup. Full sweep: 576 passed, 0 seal mismatches, 7 pre-existing gen-verilog yosys smoke failures, 0 FPGA smoke failures. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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This was referenced Jul 5, 2026
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Closing: stale wave-loop-4xx PR, superseded by later waves. Reopen if still relevant. |
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This was referenced Jul 6, 2026
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Closes #1368
Wave Loop 423 close-out. Variant B instrument depth + Variant C VCD robustness.
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