- Update .trinity/current-issue.md with W425 goal, plan, acceptance criteria

- Prepend W424 close-out and W425 setup to docs/NOW.md

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…shold, PVT process-corner monotonicity

Closes #1361

Variant C fallback (bench still blocked: P12 unwired, DLC10 cable missing,
no relay). Instrument-import depth and formal guarding only.

- cli/tri/src/fpga.rs:
  - exact-token VCD $date/$version/$comment terminator with regression test
    for embedded $end-like tokens (closes W419 report/actual gap)
  - real-valued VCD net auto-threshold from observed voltage swing
  - PVT half-period process-corner monotonicity regression test
- proofs/lean4/Trinity/TernaryFPGABoot.lean:
  - pvt_half_ns_monotone_in_process_corner (ff ≤ tt ≤ ss)
- fpga/HARDWARE_SSOT.md: §3.6.17 documenting W420 VCD/PVT improvements
- .trinity/experience.md: W420 learnings
- docs/reports: W420 report, evidence, and W421 cooperation variants

Verification:
- cargo test -p tri vcd: 13/13 PASS
- cargo test -p tri pvt: 10/10 PASS
- cargo test -p tri fpga::tests: 48/48 PASS
- lake build Trinity.TernaryFPGABoot: PASS (2967 jobs)
- ./scripts/tri test: 16 pre-existing yosys failures (#1245), no new ones

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Refs: #1362
Closes #1361

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Closes #1363

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

… PVT monotonicity, competitor snapshot

Closes #1363

Variant C fallback (bench still blocked: openFPGALoader --detect reports 0 devices).

- cli/tri/src/fpga.rs:
  - apply vcd_line_ends_with_token to $timescale terminator
  - add test_parse_vcd_timescale_with_embedded_end_token
  - add test_parse_vcd_real_auto_threshold_us_timescale
  - add test_pvt_half_ns_monotone_combined
- proofs/lean4/Trinity/TernaryFPGABoot.lean:
  - add pvt_half_ns_monotone_combined
- fpga/HARDWARE_SSOT.md: §3.6.18 documenting W421 improvements
- docs/reports/T27_VS_FORMAL_HDL_2026.md: competitor comparison
- .trinity/experience.md: W421 learnings
- docs/reports: W421 report, evidence, and W422 cooperation variants

Verification:
- cargo test -p tri vcd: 15/15 PASS
- cargo test -p tri pvt: 11/11 PASS
- cargo test -p tri fpga::tests: 51/51 PASS
- lake build Trinity.TernaryFPGABoot: PASS (2967 jobs)
- ./scripts/tri test: 16 pre-existing yosys failures (#1245), no new ones

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…escape, PVT worst-case bound

Closes #1365

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Closes #1368

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…st-case, competitor refresh (Closes #1368)

- cli/tri/src/fpga.rs: CSV ms/us/ns/sample-number normalization, VCD real-net
  slope filter, unknown timescale fallback, dumpoff/dumpon without timestamp,
  --pvt-worstcase mode; +10 regression tests (60/60 PASS).
- fpga/HARDWARE_SSOT.md: add §3.6.20 documenting W423 instrument-import depth.
- docs/reports/T27_VS_FORMAL_HDL_2026.md: refresh Sparkle/Verilean, Clash, CIRCT.
- docs/reports/WAVE_LOOP_423_REPORT.md, FPGA_LOOP_EVIDENCE_W423_2026-07-05.md,
  FPGA_LOOP_COOPERATION_W424_2026-07-05.md: W423 close-out + W424 variants.
- docs/NOW.md, .trinity/experience.md, .trinity/current-issue.md: W423 close-out
  and W424 setup.

Full sweep: 576 passed, 0 seal mismatches, 7 pre-existing gen-verilog yosys
smoke failures, 0 FPGA smoke failures.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Update .trinity/current-issue.md and cooperation file with the new W424
issue number.

Reference #1371

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…voltage units, non-blocking continue, W425 setup

- Add non-blocking wait_for_continue helper for boot-log/cold-por/cclk-sweep

- Parse CSV voltage units (v/mv) and scale to volts before threshold detection

- Embed optional PVT context + XADC placeholder into boot-log JSON

- Expand default CCLK sweep to OSCFSEL 0..7

- Add Lean 4 ProcessCorner decidability/severity helpers

- W424 report, evidence, and W425 cooperation variants

Closes #1371

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Closes #1371

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…e theorems (closes #1374)

- cli/tri/src/fpga.rs: expand cclk-sweep/smoke-gate default OSCFSEL range to 0–7
- proofs/lean4/Trinity/TernaryFPGABoot.lean: add pvt_half_ns_worst_case_is_upper_envelope
  and pvt_low_ns_worst_case_is_upper_envelope; move OSCFSEL_WORST_CASE_PVT_CONTEXT earlier
- docs/reports: W425 report, evidence, and W426 cooperation variants
- .trinity/current-issue.md + experience.md: W425 close-out learnings
- Variant C executed because P12 is still unwired and no relay gate is available

Verification: cargo test -p tri PASS, lake build PASS, tri test PASS (7 pre-existing gen-verilog yosys smoke failures unchanged)

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…e tri fpga JSON, competitor refresh (Variant C)

Wave 426 executed Variant C because the physical bench is still blocked:
P12 CCLK probe unwired, no relay gate, DLC10 missing.

Deliverables:
- proofs/lean4/Trinity/TernaryFPGABoot.lean:
  - pvt_half_ns_operating_rectangle_grid_bounded
  - pvt_low_ns_operating_rectangle_grid_bounded
  - exhaustive 75-point worst-case corner dominance proof
- cli/tri/src/fpga.rs:
  - cclk_nominal_hz mirror of the Lean CCLK table
  - pvt_envelope_margin_ns and recommendation_from_conclusion helpers
  - SweepLog, boot-log, and cold-por JSON now emit recommendation and margin
  - 8 new unit tests (101/101 pass)
- docs/reports/T27_VS_FORMAL_HDL_2026.md: Sparkle July 2026 Functional Matsuri
  talk, Clash 1.8.5 verification fixes, CIRCT/firtool notes
- docs/reports/W426_WEAK_POINTS_AND_COMPETITORS.md: updated weak-point scan
- docs/reports/WAVE_LOOP_426_REPORT.md and FPGA_LOOP_EVIDENCE_W426_2026-07-05.md
- docs/reports/FPGA_LOOP_COOPERATION_W427_2026-07-05.md: next-wave variants
- .trinity/experience.md: W426 learnings
- docs/NOW.md: W426 close-out / W427 setup
- .trinity/current-issue.md: mark Variant C acceptance criteria complete

Verification:
- cargo test -p tri: 101/101 pass
- lake build Trinity.TernaryFPGABoot: 2967 jobs, 0 errors
- ./scripts/tri test: parse/typecheck/gen/seal-verify PASS; 7 pre-existing
  gen-verilog-yosys-smoke failures (#1245) unchanged

Closes #1376

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…ga sweep-report --json, competitor refresh (Variant C)

Closes #1379

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…t-envelope --json, competitor refresh

Closes #1383

- Add four quantified OSCFSEL 0..7 PVT/transaction theorems in
  proofs/lean4/Trinity/TernaryFPGABoot.lean.
- Add --json output to tri fpga pvt-envelope with shared report builder
  and unit tests.
- Refresh T27_VS_FORMAL_HDL_2026.md with 2026 releases and emerging signals.
- Document W428 gen-verilog #1245 deferral.
- Add close-out reports and W429 cooperation variants.
- Update docs/NOW.md and .trinity/experience.md.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Sets up W429 tracking issue #1385 and default Variant C rationale.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

… --json, W429 report and W430 cooperation (Closes #1385)

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Closes #1385

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…431 cooperation\n\n- Add tri fpga read-xadc and --xadc flags on boot-log/cold-por/cclk-sweep.\n- Parse openFPGALoader --read-xadc output and embed live temp/vccint/vccaux in JSON logs.\n- Add XadcOperatingPoint formal bridge and worst-case-bound theorem in TernaryFPGABoot.lean.\n- Update fpga/HARDWARE_SSOT.md, T27_VS_FORMAL_HDL_2026.md, GEN_VERILOG_DEFECTS_REPRO.md.\n- Create WAVE_LOOP_430_REPORT.md and FPGA_LOOP_COOPERATION_W431_2026-07-01.md.\n- Verification: cargo test fpga:: 79/79, lake build pass, tri test pass except 7 pre-existing #1245 failures.\n\nCloses #1388\n\nCo-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

… 430 close-out)\n\n- Point .trinity/current-issue.md and docs/NOW.md to W431 (#1389).\n- Add W430 learnings to .trinity/experience.md.\n\nCo-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…ope, measured-to-lean --json summary hardening

Closes #1389

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…s, master-merge feasibility probe, W432 close-out artifacts

Closes #1391

- Add cclk_variant_raw_ns_per_process_corner_pvt_satisfies_flash_spec and
  cclk_variant_raw_ns_per_process_corner_pvt_implies_transaction_ok in
  proofs/lean4/Trinity/TernaryFPGABoot.lean, quantifying PVT-aware safety over
  all documented OSCFSEL values (0..7) and all process corners (ff/tt/ss).
- Probed origin/master merge and cherry-pick of 507408f; fix set 701d79b is
  on a divergent master lineage not safely reachable from wave-loop-432.
- Refresh docs/reports/T27_VS_FORMAL_HDL_2026.md and
  docs/reports/GEN_VERILOG_DEFECTS_REPRO.md with W432 triage.
- Add W432 report, evidence note, and W433 cooperation variants.
- Update docs/NOW.md and .trinity/current-issue.md for W433 (#1393).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…-merge probe, blocked bench redirect

Closes #1391

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…em, standalone snapshot, --fast suite mode

Closes #1425

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…UX independence, CI metric hardening, smoke-gate snapshots

Closes #1423

- proofs/lean4/Trinity/TernaryFPGABoot.lean: VCCAUX independence lemmas,
  BOUNDARY_HOT_LOWV_W451_* operating point/context,
  boundary_hot_lowv_w451_all_corners_transaction_ok theorem.
- bootstrap/src/suite.rs: FpgaSmokeResultBuilder, serde deny_unknown_fields
  on SuiteSummary/SuitePhaseSummary, regression tests.
- cli/tri/src/fpga.rs: deterministic snapshot tests for missing-bitstream
  and --fast skipped-standalone shapes.
- tests/fixtures/fpga/smoke-gate: committed snapshots.
- docs/reports: W451 report, evidence, plan, W452 cooperation,
  T27_VS_FORMAL_HDL_2026 refresh, GEN_VERILOG_DEFECTS_REPRO triage.
- docs/NOW.md + .trinity/current-issue.md: W451 close-out / W452 setup.

Verification: 576/576 non-smoke PASS, 7 baseline gen-verilog failures,
FPGA smoke gate acceptable, lake build PASS.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…em, adversarial VCCINT witness, OSCFSEL range gate, CI smoke-state hardening, all-ok snapshot

- Add BOUNDARY_COLD_HIGHV_W452_OPERATING_POINT and quantified transaction theorem
  boundary_cold_highv_w452_all_corners_transaction_ok over OSCFSEL 0..7 and ff/tt/ss.
- Add OUTSIDE_VCCINT_LOW_W452_OPERATING_POINT adversarial witness and prove the
  dashboard gate rejects it; add oscfsel_out_of_range_combined_check_false.
- Extend FpgaSmokeResult/SuiteSummary with passed/skipped/failed/failure_reason state.
- Add all-ok smoke-gate snapshot test + fixture.
- Refresh competitor report; mint W452 close-out artifacts and W453 cooperation.

Closes #1422

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…harden smoke-gate JSON schema, refresh competitors

- Add EnvelopeCorner inductive and BOUNDARY_HOT_HIGHV_W453 / BOUNDARY_COLD_LOWV_W453 operating points.
- Prove all_envelope_corners_w453_all_corners_transaction_ok and computable counterpart.
- Add #[serde(deny_unknown_fields)] SmokeGateReport schema on generator and consumer.
- Add unit tests for schema acceptance / unknown-field rejection on both sides.
- Refresh competitor survey; no new Lean-native ternary-FPGA competitor.
- Mint W453 report, evidence, plan, and W454 cooperation artifacts.

Closes #1421

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…1424

Closes nothing — W454 setup commit.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

…le asymmetry, bounded jitter theorems + Rust counterparts; reject master-merge as insufficient; W455 handoff

Closes #1424

- Add OUTSIDE_VCCINT_HIGH_W454_OPERATING_POINT and dashboard-gate rejection theorem
- Add cclk_oscfsel_7_duty_asymmetry_w454 and cclk_ideal_split_robust_to_1ns_jitter_w454
- Add cclk_variant_and_xadc_envelope_check Rust helper and 5 W454 unit tests
- Refresh T27_VS_FORMAL_HDL_2026.md and GEN_VERILOG_DEFECTS_REPRO.md W454 boundary
- Mint WAVE_LOOP_454_REPORT.md, FPGA_LOOP_EVIDENCE_W454, FPGA_LOOP_COOPERATION_W455
- Update NOW.md and current-issue.md for W455 (#1425) handoff

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>