feat(trios-chat): three-channel mesh chat specs + product design#56
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feat(trios-chat): three-channel mesh chat specs + product design#56gHashTag wants to merge 15 commits into
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added 15 commits
July 7, 2026 20:34
New specs (all parse OK, t27c gen-rust verified):
specs/channel_t_modem.t27 - BPSK 1200 bps, text, 10km (12 tests)
specs/channel_p_modem.t27 - QPSK 250 kbps, photo, 3km (12 tests)
specs/trng.t27 - Hardware TRNG, von Neumann, health (18 tests)
Product spec:
docs/TRIOS_CHAT_SPEC.md - Three-channel arch (T/P/V), positioning matrix,
resource allocation, competitor analysis, roadmap
Three channels:
T (text) BPSK 1200 bps 10 km 200-byte msg = 1.3 sec
P (photo) QPSK 250 kbps 3 km 100 KB JPEG = 3.2 sec
V (video) 16QAM 2 Mbps 1 km 720p live @ 500 kbps
FPGA fit: 36.3k LUT / 204 DSP / 69 BRAM (XC7Z020 budget)
phi^2 + phi^-2 = 3
New specs (7 total, all parse OK): specs/aes256_gcm.t27 - AES-256-GCM hardware engine (19 tests, 5 invariants) specs/channel_v_modem.t27 - 16-QAM 2 Mbps video channel (12 tests, 4 invariants) specs/viterbi_k5.t27 - FEC decoder K=5 R=1/2 (16 tests, 4 invariants) specs/link_negotiation.t27 - Auto channel selection by SNR (15 tests, 3 invariants) Fixes: build.rs: fixed Option/SystemTime comparison bug gen/rust/: regenerated 75 files from 75 specs Product spec: docs/TRIOS_CHAT_SPEC.md: three-channel arch + competitor matrix + roadmap M2 mesh status: M1 crypto: PASS on 3 ARM boards (X25519 + ChaCha20-Poly1305) M2 mesh: blocked by identical MAC on switch (documented) Workaround: loopback 3-node mesh on single board (tested, blocked by sshd hang) Blocker for M2: identical MAC = switch can't route between boards. Solution: per-board MAC in baked image (persistent) or USB-Ethernet adapter. phi^2 + phi^-2 = 3
New:
specs/mesh_convergence.t27 — M2 gate: ETX convergence (15 tests, 4 invariants)
tools/board_init.rs — runtime MAC/IP setter per board
tools/board-configs/uEnv-board{1,2,3}.txt — per-board U-Boot ethaddr
docs/W13_WAVE_PLAN.md — wave plan (5 deliverables)
Pipeline: 76 specs -> 76 generated files
L7 compliant: all tools in Rust, zero .sh/.py
phi^2 + phi^-2 = 3
New:
specs/chat_protocol.t27 — app-layer messaging (22 tests, 3 invariants)
msg types: text/photo/video/voice/status/ack
channel selection: auto T/P/V by msg_type + SNR
chunking: 1KB blocks for media
timestamp validation
docs/W14_WAVE_PLAN.md — UX wave (web UI, dashboard, demo)
Pipeline: 77 specs -> 77 generated
Per-board MAC configs: tools/board-configs/uEnv-board{1,2,3}.txt
Runtime MAC tool: tools/board_init (Rust, L7 compliant)
phi^2 + phi^-2 = 3
New specs: specs/reed_solomon.t27 — RS(255,223) FEC, 16 errors correctable (10 tests) specs/codec2_voice.t27 — Codec2 700-3200 bps voice, walkie-talkie (10 tests) specs/gps_pps.t27 — GPS PPS + TDMA slot coordination (11 tests) Master roadmap W15-W20: W15: Photo (Channel P, QPSK+RS) W16: Video (Channel V, OFDM+Viterbi) W17: FPGA BPSK modem (Verilog) W18: FPGA AES-256 (hardware crypto) W19: FPGA OFDM (FFT-256) W20: Integration + partner demo Pipeline: 80 specs -> 80 generated phi^2 + phi^-2 = 3
New:
specs/security_audit.t27 — security checklist (16 tests, 3 invariants)
key strength, nonce uniqueness, replay window, auth lockout
session timeout, key rotation, constant-time compare
docs/MASTER_ROADMAP_COMPLETE.md — W12 through W25, 14 waves
M1-M5 milestone mapping, critical path, resource summary
Pipeline: 81 specs -> 81 generated
phi^2 + phi^-2 = 3
New FPGA specs (gen-verilog verified):
specs/fpga_bpsk_tx.t27 — BPSK TX FSM, 16-bit IQ, preamble (12 tests)
specs/fpga_aes_sbox.t27 — AES-256 round controller, S-box (12 tests)
Golden pipeline proven: .t27 -> t27c gen-verilog -> Verilog
-> t27c gen-rust -> Rust
Pipeline: 83 specs -> 83 Rust + Verilog generation verified
phi^2 + phi^-2 = 3
Final spec batch: specs/integration.t27 — M1-M5 milestone gates (15 tests, 4 invariants) specs/photo_transfer.t27 — JPEG chunking + RS reassembly (13 tests, 2 invariants) specs/video_stream.t27 — H.264 GOP chunking, latency (13 tests, 3 invariants) FULL SPEC INVENTORY: 86 .t27 specs 86 generated Rust files 904 test blocks 63 invariant blocks Verilog generation proven (FpgaBpskTx, FpgaAesSbox) COVERAGE: Channel T (BPSK text) ✓ fully spec'd Channel P (QPSK photo) ✓ fully spec'd Channel V (16-QAM video) ✓ fully spec'd AES-256-GCM ✓ fully spec'd TRNG ✓ fully spec'd Viterbi FEC ✓ fully spec'd Reed-Solomon FEC ✓ fully spec'd Codec2 voice ✓ fully spec'd GPS PPS TDMA ✓ fully spec'd Link negotiation ✓ fully spec'd Chat protocol ✓ fully spec'd Mesh convergence ✓ fully spec'd Security audit ✓ fully spec'd Integration M1-M5 ✓ fully spec'd phi^2 + phi^-2 = 3
New: tools/tri.rs — unified CLI (status, deploy, test, regen, rf, mesh) gen/verilog/*.v — Verilog HDL from t27c gen-verilog (12 modules) tri CLI commands: tri status — ping + kernel + AD9361 + RSSI + meshd state tri deploy — cross-compile + SCP to all 3 boards tri test — E2E + M1 crypto smoke tri regen — specs/*.t27 -> gen/rust/ + gen/verilog/ tri rf 2.4 — configure AD9361 on all boards tri mesh — start 3-node mesh Pipeline complete: 86 .t27 specs -> 86 gen/rust/*.rs + 12 gen/verilog/*.v 904 tests, 63 invariants L7 compliant (all Rust, zero .sh/.py) phi^2 + phi^-2 = 3
Added to constitutional law: Article V: Multi-Board Boot Procedure (CRITICAL) Documents the WORKING recipe proven 2026-07-07: - 5 SD card files (BOOT.BIN, uImage, DTB, ramdisk, uEnv.txt) - Boot switch QSPI/SD, USB power, Ethernet - SSH: sshpass -p analog ssh -o PubkeyAuthentication=no root@192.168.1.1N - Multi-board: ip addr add .11/.12/.13, then del .10 - WARNING: ethaddr in uEnv does NOT propagate to Linux (DT MAC wins) - WARNING: do NOT delete .10 while SSH'd through it 3 boards confirmed alive simultaneously: 192.168.1.11 Linux 5.10.0 AD9361=ad9361-phy 192.168.1.12 Linux 5.10.0 AD9361=ad9361-phy 192.168.1.13 Linux 5.10.0 AD9361=ad9361-phy phi^2 + phi^-2 = 3
Loopback test on P201Mini: 3 meshd instances, unique IDs 11/12/13 ETX convergence: inf -> 1.00 in ~600ms Message delivery: node 11 -> node 13 DELIVERED Multi-hop forwarding: Forwarded(13) Blocked: Multi-board mesh needs unique MAC (same MAC = switch can't route) Solution: baked image with persistent MAC per board phi^2 + phi^-2 = 3
…lved) SOUL.md: Article V rewritten with PROVEN multi-board recipe - uEnv.txt ethaddr + boardargs (unique MAC + IP at kernel boot) - Flash via SSH (mount /dev/mmcblk0p1, NO card reader) - ARP dance for runtime separation - All B1-B10 bottlenecks documented tri CLI v3: status — ping + MAC + kernel + AD9361 + meshd separate — ARP dance IP split flash-uenv — Modify SD card via SSH (NEW!) deploy — Push binary test — M1 crypto mesh — 3-node loopback convergence regen — specs -> Rust + Verilog rf — AD9361 config Experience saved: .trinity/experience/w12-marathon.json phi^2 + phi^-2 = 3
CRITICAL FINDING: P201Mini auto-detects SD card regardless of switch. JTAG position + SD card = boots from SD perfectly. Do NOT tell user to change boot switch for SD boot. Board 1 death cause updated: - NOT boot switch (was in JTAG, works fine) - MMU stuck from JTAG experiments (ps7_init, kernel load) - Recovery needs Vivado/XSDB or JTAG MMU disable Proven recipe: vendor BOOT.BIN (2.9MB) + ethaddr change only phi^2 + phi^-2 = 3
Comprehensive report covering 20+ hour session: P1: Boards dead (POR cleared, FSBL parks) P2: QSPI driver bug (W25Q256 vs N25Q256A) P3: JTAG DAP intermittent (adapter usb location) P4: MMU blocks DAP access P5: Identical MAC collision (6 fix attempts documented) P6: Kuiper vs Vendor BOOT.BIN P7: Board 1 JTAG MMU damage (permanent) P8: SD card wear (20+ cycles) P9: Boot switch irrelevant (Article VIII) P10: macOS limitations (raw disk, FTDI conflict, sshpass) Solutions that worked + remaining blockers + tri CLI commands. phi^2 + phi^-2 = 3
PROVEN on board 3 (2026-07-08): Boot switch in JTAG position SD card inserted → Linux boots from SD → MAC 02:00:00:00:00:03 (from uEnv.txt) → AD9361 detected, SSH works Boot switch position is IRRELEVANT for SD boot on P201Mini. BootROM auto-detects SD card presence regardless of switch. Also updated: - Do NOT modify ramdisk (mkimage CRC issues) - sshpass needs -o PreferredAuthentications=password - Vendor BOOT.BIN = correct PL Ethernet (Kuiper = broken) phi^2 + phi^-2 = 3
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What
Specs for three-channel mesh chat (T/P/V) with FPGA PHY:
specs/channel_t_modem.t27— BPSK 1200 bps text channel (12 tests, 4 invariants)specs/channel_p_modem.t27— QPSK 250 kbps photo channel (12 tests, 4 invariants)specs/trng.t27— Hardware TRNG for AES key generation (18 tests, 4 invariants)docs/TRIOS_CHAT_SPEC.md— Full product design + competitor analysisWhy
800x faster photo than Meshtastic (3 sec vs 40 min).
Hardware crypto in PL (line-rate AES-256-GCM).
TRNG for regulator-compliant entropy.
Programmable PHY (upgrade without hardware change).
Pipeline compliance
phi^2 + phi^-2 = 3