blink.v

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// blink v1.0.0 - FPGA Verilog from .vibee specification
// ═══════════════════════════════════════════════════════════════════════════════
//
// Golden Identity: φ² + 1/φ² = 3
//
// DO NOT EDIT - This file is auto-generated by VIBEE
//
// Target:   xilinx (50 MHz)
// ═══════════════════════════════════════════════════════════════════════════════

`timescale 1ns / 1ps

module blink (
input  wire clk,
output  wire led
);

          // 26-bit counter for slower, more visible blink
      // LED is ACTIVE-LOW: 0 = ON, 1 = OFF (needs inversion!)
      // Bit 25: 2^25 / 50MHz ≈ 0.67 seconds period = ~1.5 Hz blink
      reg [25:0] counter = 26'h0;

      always @(posedge clk) begin
          counter <= counter + 1'b1;
      end

      // Invert for active-low LED: ~counter[25]
      assign led = ~counter[25];


endmodule