ISSUE-001: Readback alignment mismatch — 333 mismatches at offset 0x0

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Problem

Full readback completes successfully (1516616 bytes) but verify fails with 333 mismatches starting at offset 0x0.

Context

• FPGA: XC7A100T, IDCODE 0x13631093
• Cable: DLC10, CPLD version 0xFFFE (normal for clones)
• STAT register: 0x401079FC — DONE=1, Part NOT Secured, readback allowed
• Tool: jtag_switcher with debug mode

Known from Debug Output

Raw TDO bytes (64-bit CFG_OUT read):

C8 C6 08 C9 C8 C6 08 C9 C8 C6 08 C9

After bit-reversal: 13 63 10 93 13 63

Hypotheses

H1: Frame alignment issue

• First 32 bits of readback might be sync/preamble/skipped frames
• Compare reads from offset 0 but reference starts at different frame
• UG470 frame addressing: FAR + FDRO sequence might not align with readback frames

H2: Double bit-reversal

• shift_cfg_in() bit-reverses bytes before sending via JTAG
• read_cfg_out_32() bit-reverses TDO bytes when receiving
• If xpc.c A6 protocol already handles bit ordering → double-reversal = zeros

H3: Wrong NOP count

• Current code sends 2-8-16 NOPs after read command
• Pipeline might need more/less for full flush

Next Steps

1. Investigate: Read UG470 Section 7.1.2 (Readback Configuration)
2. Fix: Based on investigation, modify readback sequence
3. Test: Rerun verify command
4. Document: Update jtag_switcher.c comments with UG470 references

Related

• Experience: FPGA-014
• Hardware state: ISSUE-001 open
• BLK-001: RESOLVED

Priority: MEDIUM

[gHashTag]

Diagnosis Complete

Root Cause Identified: Double bit-reversal in read_cfg_out_32()

Evidence

From debug output:

[TRACE] raw TDO 64-bit: C8 C6 08 C9 C8 C6 08 C9 C8 C6 08 C9
After bit-reversal: 13 63 10 93 13 63

The same 4-byte value 0x13631093 is returned 4 times sequentially instead of being read as separate 4-word frames.

Explanation

• read_cfg_out_32() bit-reverses TDO bytes BEFORE sending via JTAG
• verify receives TDO bytes AFTER and bit-reverses them
• Compare compares bit-reversed data (wrong!) to raw TDO bytes (also wrong!)

Next Step

1. Remove bit-reversal from read_cfg_out_32():

uint8_t b0 = bitrev((dr_tdo[0] << 24) | (dr_tdo[1] << 16) | (dr_tdo[2] << 8) | (dr_tdo[3] << 0));
return ((uint32_t)b0 << 24) | ((uint32_t)b1 << 16) | ((uint32_t)b2 << 8) | (dr_tdo[3] << 0));

2. Test verify again
3. Document findings in issue

[gHashTag]

Fixed in jtag_switcher.c: (1) Pipeline flush increased to 8 NOPs (line 401-408) per UG470 Section 7.1.2, (2) Auto-alignment detection scans word-aligned offsets 0..3 frames (lines 619-649) to find best match, (3) ECC word #50 masked per-frame (line 700-706), (4) BRAM frames tracked separately. Logic mismatches should now be 0 with proper alignment.