Performance: Fields are organized for cache efficiency

Author: gdevic

src/ClassLogic.cpp

@@ -276,7 +276,7 @@ Logic *ClassNetlist::parse(Logic *node, int depth)
     // Copy the list of transistors for which this net is either a source or a drain, but skip over transistors already visited
     // While copying, make sure c1 contains our primary net number, and c2 is "the other end" net
     node->trans.reserve(net0.c1c2s.size());
-    for (const Trans *t : net0.c1c2s)
+    for (Trans *t : net0.c1c2s)
     {
         if (!visitedTrans.contains(t->id)) // Skip over transistors already visited
         {

src/ClassNetlist.cpp

@@ -407,9 +407,9 @@ const QStringList ClassNetlist::get(const QVector<net_t> &nets)
 const QVector<net_t> ClassNetlist::netsDriving(net_t n)
 {
     QVector<net_t> nets;
-    const QVector<Trans *> &gates = m_netlist[n].gates;
+    const QVector<Trans*> &gates = m_netlist[n].gates;
 
-    for (const auto t : gates)
+    for (Trans *t : gates)
     {
         if ((t->c1 > 2) && !nets.contains(t->c1)) // c1 is the source
             nets.append(t->c1);
@@ -426,9 +426,11 @@ const QVector<net_t> ClassNetlist::netsDriving(net_t n)
 const QVector<net_t> ClassNetlist::netsDriven(net_t n)
 {
     QVector<net_t> nets;
-    for (auto &t : m_netlist[n].c1c2s)
+    for (Trans *t : m_netlist[n].c1c2s)
+    {
         if (!nets.contains(t->gate))
             nets.append(t->gate);
+    }
     std::sort(nets.begin(), nets.end()); // Sorting numbers only
     return nets;
 }
@@ -439,8 +441,8 @@ const QVector<net_t> ClassNetlist::netsDriven(net_t n)
 inline pin_t ClassNetlist::getNetStateEx(net_t n)
 {
     // Every transistor in the contributing nets needs to be off for this net to be hi-Z
-    for (auto &tran : m_netlist[n].c1c2s)
-        if (tran->on) return !!m_netlist[n].state;
+    for (Trans *t : m_netlist[n].c1c2s)
+        if (t->on) return !!m_netlist[n].state;
     // If nothing is explicitly driving this net, it will be "1" if it has an internal pullup
     if (m_netlist[n].hasPullup)
         return 1;
@@ -520,12 +522,12 @@ const QString ClassNetlist::netInfo(net_t net)
     {
         // Transistor numbers for which this net is either a source or a drain
         QStringList c1c2s;
-        for (auto &t : m_netlist[net].c1c2s)
-            c1c2s.append(QString::number(t - &m_transdefs[0]));
+        for (Trans *t : m_netlist[net].c1c2s)
+            c1c2s.append(QString::number(t->id));
         // Transistor numbers for which this net is a gate
         QStringList gates;
-        for (auto &t : m_netlist[net].gates)
-            gates.append(QString::number(t - &m_transdefs[0]));
+        for (Trans *t : m_netlist[net].gates)
+            gates.append(QString::number(t->id));
         // Limit printing up to 20 gate nets which is more than a practical limit.
         // This prevents large nets like clk to take over the log window
         if (gates.count() > 20)

src/ClassNetlist.h

@@ -6,19 +6,24 @@
 #include <QHash>
 
 // Contains individual transistor definition
+// Fields are organized for cache efficiency: hot data (frequently accessed) first
 struct Trans
 {
-    tran_t id;                          // Transistor number
-    net_t gate;                         // Net connected to its gate
-    net_t c1, c2;                       // Connections 1, 2 (source, drain) nets
-    bool on {false};                    // Is the transistor on?
+    // Hot data - accessed in critical path (recalcNet, addNetToGroup)
+    bool on {false};                    // Is the transistor on? (1 byte)
+    // Padding for alignment (1 byte) - compiler will add this automatically
+    net_t c1, c2;                       // Connections 1, 2 (source, drain) nets (4 bytes total)
+
+    // Cold data - rarely accessed in hot path
+    net_t gate;                         // Net connected to its gate (2 bytes)
+    tran_t id;                          // Transistor number (2 bytes)
 };
 
 // Contains netlist net definition: net is a trace with equal potential and it connects a number of transistors
 struct Net
 {
-    QVector<Trans *> gates;             // The list of transistors for which this net is a gate
-    QVector<Trans *> c1c2s;             // The list of transistors for which this net is either a source or a drain
+    QVector<Trans*> gates;              // Transistors for which this net is a gate
+    QVector<Trans*> c1c2s;              // Transistors for which this net is either a source or a drain
     bool state {false};                 // The voltage on the net is high (if not floating)
     bool floats {false};                // Net can float (used with ab, db, mreq, iorq, rd, wr to read hi-Z state)
     bool isHigh {false};                // Net is being pulled high

src/ClassSimZ80.cpp

@@ -357,7 +357,7 @@ inline bool ClassSimZ80::getNetValue()
 #if 0
         // We just want to pick the larger, or "stronger" net, assuming that one would have more transistor connections
         //auto conn = net.gates.count() + net.c1c2s.count();
-        auto conn = net.c1c2s.count();
+        //auto conn = net.c1c2s.count();
         auto conn = net.gates.count();
         if (conn > max_conn)
         {
@@ -416,7 +416,7 @@ inline void ClassSimZ80::recalcNet(net_t n)
         net.state = newState;
 
         if (net.state)
-            for (Trans *&t : net.gates)
+            for (Trans *t : net.gates)
             {
                 if (!t->on)
                 {
@@ -425,7 +425,7 @@ inline void ClassSimZ80::recalcNet(net_t n)
                 }
             }
         else
-            for (Trans *&t : net.gates)
+            for (Trans *t : net.gates)
             {
                 if (t->on)
                 {
@@ -447,12 +447,12 @@ inline void ClassSimZ80::recalcNet(net_t n)
         Net &net = m_netlist[i];
         if (net.state == newState) continue;
         net.state = newState;
-        for (int i = 0; i < net.gates.count(); i++)
+        for (Trans *t : net.gates)
         {
             if (net.state)
-                setTransOn(net.gates[i]);
+                setTransOn(t);
             else
-                setTransOff(net.gates[i]);
+                setTransOff(t);
         }
     }
 }
@@ -544,7 +544,8 @@ inline void ClassSimZ80::addNetToGroup(net_t n)
     setBit(m_groupBitset, n);
     m_group[m_groupIndex++] = n;
     if (Q_UNLIKELY((n == ngnd) || (n == npwr))) return;
-    for (auto &t : m_netlist[n].c1c2s)
+
+    for (Trans *t : m_netlist[n].c1c2s)
     {
         if (!t->on) continue;
         net_t other = 0;
@@ -560,7 +561,8 @@ inline void ClassSimZ80::addNetToGroup(net_t n)
     if (group.contains(n)) return;
     group.append(n);
     if (Q_UNLIKELY((n == ngnd) || (n == npwr))) return;
-    for (auto &t : m_netlist[n].c1c2s)
+
+    for (Trans *t : m_netlist[n].c1c2s)
     {
         if (!t->on) continue;
         net_t other = 0;