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dalancedalance
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Add Veryl
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‎.gitmodules‎

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[submodule "vendor/grammars/verilog.tmbundle"]
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path = vendor/grammars/verilog.tmbundle
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url = https://github.com/textmate/verilog.tmbundle
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[submodule "vendor/grammars/veryl"]
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path = vendor/grammars/veryl
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url = https://github.com/veryl-lang/veryl.git
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[submodule "vendor/grammars/vsc-ember-syntax"]
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path = vendor/grammars/vsc-ember-syntax
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url = https://github.com/lifeart/vsc-ember-syntax.git

‎grammars.yml‎

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@@ -1164,6 +1164,8 @@ vendor/grammars/typst-grammar:
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- source.typst
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vendor/grammars/verilog.tmbundle:
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- source.verilog
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vendor/grammars/veryl:
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- source.veryl
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vendor/grammars/vsc-ember-syntax:
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- inline.hbs
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- inline.template

‎lib/linguist/languages.yml‎

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@@ -8103,6 +8103,14 @@ Verilog:
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codemirror_mode: verilog
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codemirror_mime_type: text/x-verilog
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language_id: 387
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Veryl:
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type: programming
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color: "#27a357"
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extensions:
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- ".veryl"
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tm_scope: source.veryl
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ace_mode: text
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language_id: 735748450
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Vim Help File:
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type: prose
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color: "#199f4b"

‎samples/Veryl/fifo.veryl‎

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pub module fifo #(
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param WIDTH : u32 = 8 ,
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param TYPE : type = logic<WIDTH> ,
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param DEPTH : u32 = 8 ,
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param THRESHOLD : u32 = DEPTH ,
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param FLAG_FF_OUT : bool = true ,
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param DATA_FF_OUT : bool = true ,
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param RESET_RAM : bool = false ,
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param RESET_DATA_FF : bool = true ,
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param CLEAR_DATA : bool = false ,
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param PUSH_ON_CLEAR : bool = false ,
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param MATCH_COUNT_WIDTH: u32 = 0 ,
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const COUNTER : type = logic<$clog2(DEPTH + 1)>,
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) (
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i_clk : input clock ,
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i_rst : input reset ,
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i_clear : input logic ,
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o_empty : output logic ,
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o_almost_full: output logic ,
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o_full : output logic ,
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o_word_count : output COUNTER,
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i_push : input logic ,
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i_data : input TYPE ,
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i_pop : input logic ,
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o_data : output TYPE ,
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) {
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const RAM_WORDS: u32 = if DATA_FF_OUT ? DEPTH - 1 : DEPTH;
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var clear_data: logic;
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always_comb {
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clear_data = CLEAR_DATA && i_clear;
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}
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//--------------------------------------------------------------
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// controller
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//--------------------------------------------------------------
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const RAM_POINTER_WIDTH: u32 = if RAM_WORDS >= 2 ? $clog2(RAM_WORDS) : 1;
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var write_pointer: logic<RAM_POINTER_WIDTH>;
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var write_to_ff : logic ;
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var write_to_ram : logic ;
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var read_pointer : logic<RAM_POINTER_WIDTH>;
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var read_from_ram: logic ;
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inst u_controller: fifo_controller #(
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TYPE ,
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DEPTH ,
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THRESHOLD ,
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FLAG_FF_OUT ,
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DATA_FF_OUT ,
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PUSH_ON_CLEAR ,
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RAM_WORDS ,
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RAM_POINTER_WIDTH ,
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MATCH_COUNT_WIDTH ,
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) (
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i_clk ,
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i_rst ,
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i_clear ,
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o_empty ,
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o_almost_full ,
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o_full ,
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i_push ,
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i_data ,
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i_pop ,
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o_word_count ,
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o_write_pointer: write_pointer,
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o_write_to_ff : write_to_ff ,
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o_write_to_ram : write_to_ram ,
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o_read_pointer : read_pointer ,
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o_read_from_ram: read_from_ram,
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);
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//--------------------------------------------------------------
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// RAM
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//--------------------------------------------------------------
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var ram_read_data: TYPE;
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if RAM_WORDS >= 1 :g_ram {
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inst u_ram: ram #(
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WORD_SIZE : RAM_WORDS ,
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ADDRESS_WIDTH: RAM_POINTER_WIDTH,
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DATA_TYPE : TYPE ,
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BUFFER_OUT : 0 ,
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USE_RESET : RESET_RAM ,
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) (
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i_clk ,
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i_rst ,
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i_clr : clear_data ,
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i_mea : '1 ,
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i_wea : write_to_ram ,
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i_adra: write_pointer,
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i_da : i_data ,
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i_meb : '1 ,
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i_adrb: read_pointer ,
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o_qb : ram_read_data,
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);
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} else :g_no_ram {
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always_comb {
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ram_read_data = 0 as TYPE;
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}
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}
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//--------------------------------------------------------------
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// output control
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//--------------------------------------------------------------
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if DATA_FF_OUT :g_data_out {
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var data_out: TYPE;
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always_comb {
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o_data = data_out;
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}
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if RESET_DATA_FF :g {
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always_ff {
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if_reset {
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data_out = 0 as TYPE;
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} else if clear_data {
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data_out = 0 as TYPE;
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} else if write_to_ff {
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data_out = i_data;
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} else if read_from_ram {
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data_out = ram_read_data;
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}
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}
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} else {
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always_ff {
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if clear_data {
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data_out = 0 as TYPE;
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} else if write_to_ff {
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data_out = i_data;
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} else if read_from_ram {
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data_out = ram_read_data;
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}
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}
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}
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} else {
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always_comb {
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o_data = ram_read_data;
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}
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}
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}

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