Copybara import of the project:

ken-unger · xnnpack-bot · commit ae2264543dae · 2026-04-30T10:54:42.000-07:00
-- 0cd97f2 by Ken Unger <ken.j.unger@gmail.com>: add rvv support for f16-vcmul -- 1f8d093 by Ken Unger <ken.j.unger@gmail.com>: add rvv support for f16-vcmul -- 64d21ff by Ken Unger <ken.j.unger@gmail.com>: handle unconfigured f16-vcmul kernel -- 8b3bda4 by Ken Unger <ken.j.unger@gmail.com>: update-microkernels FUTURE_COPYBARA_INTEGRATE_REVIEW=#9971 from ken-unger:f16-vcmul-rvv 8b3bda4 PiperOrigin-RevId: 907284990
diff --git a/cmake/gen/rvv_microkernels.cmake b/cmake/gen/rvv_microkernels.cmake
@@ -69,8 +69,8 @@ SET(PROD_RVV_MICROKERNEL_SRCS
   src/f32-vcopysign/gen/f32-vcopysignc-rvv-u8v.c
   src/f32-vcopysign/gen/f32-vrcopysignc-rvv-u8v.c
   src/f32-vcos/gen/f32-vcos-rvv-rational-5-4-div-u8v.c
-  src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u8v.c
   src/f32-velu/gen/f32-velu-rvv-rr2-p6-u4v.c
+  src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u8v.c
   src/f32-vgelu/gen/f32-vgelu-rvv-rational-12-10-div-u4v.c
   src/f32-vhswish/gen/f32-vhswish-rvv-u4v.c
   src/f32-vlog/gen/f32-vlog-rvv-rational-3-3-div-u8v.c
@@ -238,12 +238,12 @@ SET(NON_PROD_RVV_MICROKERNEL_SRCS
   src/f32-vcos/gen/f32-vcos-rvv-rational-5-4-div-u1v.c
   src/f32-vcos/gen/f32-vcos-rvv-rational-5-4-div-u2v.c
   src/f32-vcos/gen/f32-vcos-rvv-rational-5-4-div-u4v.c
-  src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u1v.c
-  src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u2v.c
-  src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u4v.c
   src/f32-velu/gen/f32-velu-rvv-rr2-p6-u1v.c
   src/f32-velu/gen/f32-velu-rvv-rr2-p6-u2v.c
   src/f32-velu/gen/f32-velu-rvv-rr2-p6-u8v.c
+  src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u1v.c
+  src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u2v.c
+  src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u4v.c
   src/f32-vgelu/gen/f32-vgelu-rvv-rational-12-10-div-u1v.c
   src/f32-vgelu/gen/f32-vgelu-rvv-rational-12-10-div-u2v.c
   src/f32-vgelu/gen/f32-vgelu-rvv-rational-12-10-div-u8v.c
diff --git a/cmake/gen/rvvfp16arith_microkernels.cmake b/cmake/gen/rvvfp16arith_microkernels.cmake
@@ -53,8 +53,9 @@ SET(PROD_RVVFP16ARITH_MICROKERNEL_SRCS
   src/f16-vbinary/gen/f16-vsub-rvvfp16arith-u8v.c
   src/f16-vbinary/gen/f16-vsubc-rvvfp16arith-u8v.c
   src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u8v.c
-  src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u2v.c
+  src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u2v.c
   src/f16-velu/gen/f16-velu-rvvfp16arith-rr1-p3-u2v.c
+  src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u2v.c
   src/f16-vhswish/gen/f16-vhswish-rvvfp16arith-u8v.c
   src/f16-vlrelu/gen/f16-vlrelu-rvvfp16arith-u8v.c
   src/f16-vmulcaddc/gen/f16-vmulcaddc-c4v-minmax-rvvfp16arith-2x.c
@@ -63,9 +64,9 @@ SET(PROD_RVVFP16ARITH_MICROKERNEL_SRCS
   src/f16-vrnd/gen/f16-vrndu-rvvfp16arith-u8v.c
   src/f16-vrnd/gen/f16-vrndz-rvvfp16arith-u8v.c
   src/f16-vrsqrt/gen/f16-vrsqrt-rvvfp16arith-rsqrt-u4v.c
+  src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u2v.c
   src/f16-vsqrt/gen/f16-vsqrt-rvvfp16arith-sqrt-u8v.c
   src/f16-vtanh/gen/f16-vtanh-rvvfp16arith-expm1minus-rr1-p3h2ts-div-u2v.c
-  src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u2v.c
   src/f16-vunary/gen/f16-vabs-rvvfp16arith-u8v.c
   src/f16-vunary/gen/f16-vneg-rvvfp16arith-u8v.c
   src/f16-vunary/gen/f16-vsqr-rvvfp16arith-u8v.c
@@ -160,10 +161,12 @@ SET(NON_PROD_RVVFP16ARITH_MICROKERNEL_SRCS
   src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u1v.c
   src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u2v.c
   src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u4v.c
-  src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u1v.c
-  src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u4v.c
+  src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u1v.c
+  src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u4v.c
   src/f16-velu/gen/f16-velu-rvvfp16arith-rr1-p3-u1v.c
   src/f16-velu/gen/f16-velu-rvvfp16arith-rr1-p3-u4v.c
+  src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u1v.c
+  src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u4v.c
   src/f16-vhswish/gen/f16-vhswish-rvvfp16arith-u4v.c
   src/f16-vlrelu/gen/f16-vlrelu-rvvfp16arith-u4v.c
   src/f16-vmulcaddc/gen/f16-vmulcaddc-c8v-minmax-rvvfp16arith-2x.c
@@ -172,11 +175,11 @@ SET(NON_PROD_RVVFP16ARITH_MICROKERNEL_SRCS
   src/f16-vrnd/gen/f16-vrndu-rvvfp16arith-u4v.c
   src/f16-vrnd/gen/f16-vrndz-rvvfp16arith-u4v.c
   src/f16-vrsqrt/gen/f16-vrsqrt-rvvfp16arith-rsqrt-u2v.c
+  src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u1v.c
+  src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u4v.c
   src/f16-vsqrt/gen/f16-vsqrt-rvvfp16arith-sqrt-u4v.c
   src/f16-vtanh/gen/f16-vtanh-rvvfp16arith-expm1minus-rr1-p3h2ts-div-u1v.c
   src/f16-vtanh/gen/f16-vtanh-rvvfp16arith-expm1minus-rr1-p3h2ts-div-u4v.c
-  src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u1v.c
-  src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u4v.c
   src/f16-vunary/gen/f16-vabs-rvvfp16arith-u1v.c
   src/f16-vunary/gen/f16-vabs-rvvfp16arith-u2v.c
   src/f16-vunary/gen/f16-vabs-rvvfp16arith-u4v.c
diff --git a/gen/rvv_microkernels.bzl b/gen/rvv_microkernels.bzl
@@ -65,8 +65,8 @@ PROD_RVV_MICROKERNEL_SRCS = [
     "src/f32-vcopysign/gen/f32-vcopysignc-rvv-u8v.c",
     "src/f32-vcopysign/gen/f32-vrcopysignc-rvv-u8v.c",
     "src/f32-vcos/gen/f32-vcos-rvv-rational-5-4-div-u8v.c",
-    "src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u8v.c",
     "src/f32-velu/gen/f32-velu-rvv-rr2-p6-u4v.c",
+    "src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u8v.c",
     "src/f32-vgelu/gen/f32-vgelu-rvv-rational-12-10-div-u4v.c",
     "src/f32-vhswish/gen/f32-vhswish-rvv-u4v.c",
     "src/f32-vlog/gen/f32-vlog-rvv-rational-3-3-div-u8v.c",
@@ -235,12 +235,12 @@ NON_PROD_RVV_MICROKERNEL_SRCS = [
     "src/f32-vcos/gen/f32-vcos-rvv-rational-5-4-div-u1v.c",
     "src/f32-vcos/gen/f32-vcos-rvv-rational-5-4-div-u2v.c",
     "src/f32-vcos/gen/f32-vcos-rvv-rational-5-4-div-u4v.c",
-    "src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u1v.c",
-    "src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u2v.c",
-    "src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u4v.c",
     "src/f32-velu/gen/f32-velu-rvv-rr2-p6-u1v.c",
     "src/f32-velu/gen/f32-velu-rvv-rr2-p6-u2v.c",
     "src/f32-velu/gen/f32-velu-rvv-rr2-p6-u8v.c",
+    "src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u1v.c",
+    "src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u2v.c",
+    "src/f32-vexp/gen/f32-vexp-rvv-rational-3-2-div-u4v.c",
     "src/f32-vgelu/gen/f32-vgelu-rvv-rational-12-10-div-u1v.c",
     "src/f32-vgelu/gen/f32-vgelu-rvv-rational-12-10-div-u2v.c",
     "src/f32-vgelu/gen/f32-vgelu-rvv-rational-12-10-div-u8v.c",
diff --git a/gen/rvvfp16arith_microkernels.bzl b/gen/rvvfp16arith_microkernels.bzl
@@ -49,8 +49,9 @@ PROD_RVVFP16ARITH_MICROKERNEL_SRCS = [
     "src/f16-vbinary/gen/f16-vsub-rvvfp16arith-u8v.c",
     "src/f16-vbinary/gen/f16-vsubc-rvvfp16arith-u8v.c",
     "src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u8v.c",
-    "src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u2v.c",
+    "src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u2v.c",
     "src/f16-velu/gen/f16-velu-rvvfp16arith-rr1-p3-u2v.c",
+    "src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u2v.c",
     "src/f16-vhswish/gen/f16-vhswish-rvvfp16arith-u8v.c",
     "src/f16-vlrelu/gen/f16-vlrelu-rvvfp16arith-u8v.c",
     "src/f16-vmulcaddc/gen/f16-vmulcaddc-c4v-minmax-rvvfp16arith-2x.c",
@@ -59,9 +60,9 @@ PROD_RVVFP16ARITH_MICROKERNEL_SRCS = [
     "src/f16-vrnd/gen/f16-vrndu-rvvfp16arith-u8v.c",
     "src/f16-vrnd/gen/f16-vrndz-rvvfp16arith-u8v.c",
     "src/f16-vrsqrt/gen/f16-vrsqrt-rvvfp16arith-rsqrt-u4v.c",
+    "src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u2v.c",
     "src/f16-vsqrt/gen/f16-vsqrt-rvvfp16arith-sqrt-u8v.c",
     "src/f16-vtanh/gen/f16-vtanh-rvvfp16arith-expm1minus-rr1-p3h2ts-div-u2v.c",
-    "src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u2v.c",
     "src/f16-vunary/gen/f16-vabs-rvvfp16arith-u8v.c",
     "src/f16-vunary/gen/f16-vneg-rvvfp16arith-u8v.c",
     "src/f16-vunary/gen/f16-vsqr-rvvfp16arith-u8v.c",
@@ -157,10 +158,12 @@ NON_PROD_RVVFP16ARITH_MICROKERNEL_SRCS = [
     "src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u1v.c",
     "src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u2v.c",
     "src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u4v.c",
-    "src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u1v.c",
-    "src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u4v.c",
+    "src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u1v.c",
+    "src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u4v.c",
     "src/f16-velu/gen/f16-velu-rvvfp16arith-rr1-p3-u1v.c",
     "src/f16-velu/gen/f16-velu-rvvfp16arith-rr1-p3-u4v.c",
+    "src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u1v.c",
+    "src/f16-vgelu/gen/f16-vgelu-rvvfp16arith-rational-6-4-div-u4v.c",
     "src/f16-vhswish/gen/f16-vhswish-rvvfp16arith-u4v.c",
     "src/f16-vlrelu/gen/f16-vlrelu-rvvfp16arith-u4v.c",
     "src/f16-vmulcaddc/gen/f16-vmulcaddc-c8v-minmax-rvvfp16arith-2x.c",
@@ -169,11 +172,11 @@ NON_PROD_RVVFP16ARITH_MICROKERNEL_SRCS = [
     "src/f16-vrnd/gen/f16-vrndu-rvvfp16arith-u4v.c",
     "src/f16-vrnd/gen/f16-vrndz-rvvfp16arith-u4v.c",
     "src/f16-vrsqrt/gen/f16-vrsqrt-rvvfp16arith-rsqrt-u2v.c",
+    "src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u1v.c",
+    "src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u4v.c",
     "src/f16-vsqrt/gen/f16-vsqrt-rvvfp16arith-sqrt-u4v.c",
     "src/f16-vtanh/gen/f16-vtanh-rvvfp16arith-expm1minus-rr1-p3h2ts-div-u1v.c",
     "src/f16-vtanh/gen/f16-vtanh-rvvfp16arith-expm1minus-rr1-p3h2ts-div-u4v.c",
-    "src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u1v.c",
-    "src/f16-vsigmoid/gen/f16-vsigmoid-rvvfp16arith-rr2-p2-u4v.c",
     "src/f16-vunary/gen/f16-vabs-rvvfp16arith-u1v.c",
     "src/f16-vunary/gen/f16-vabs-rvvfp16arith-u2v.c",
     "src/f16-vunary/gen/f16-vabs-rvvfp16arith-u4v.c",
diff --git a/scripts/generate-f32-vcmul.sh b/scripts/generate-f32-vcmul.sh
@@ -43,6 +43,10 @@ tools/xngen src/f32-vcmul/rvv.c.in -D LMUL=1 -o src/f32-vcmul/gen/f32-vcmul-rvv-
 tools/xngen src/f32-vcmul/rvv.c.in -D LMUL=2 -o src/f32-vcmul/gen/f32-vcmul-rvv-u2v.c &
 tools/xngen src/f32-vcmul/rvv.c.in -D LMUL=4 -o src/f32-vcmul/gen/f32-vcmul-rvv-u4v.c &
 
+tools/xngen src/f16-vcmul/rvv.c.in -D LMUL=1 -o src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u1v.c &
+tools/xngen src/f16-vcmul/rvv.c.in -D LMUL=2 -o src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u2v.c &
+tools/xngen src/f16-vcmul/rvv.c.in -D LMUL=4 -o src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u4v.c &
+
 #################################### Scalar ###################################
 tools/xngen src/f32-vcmul/scalar.c.in -D BATCH_TILE=1 -o src/f32-vcmul/gen/f32-vcmul-scalar-u1.c &
 tools/xngen src/f32-vcmul/scalar.c.in -D BATCH_TILE=2 -o src/f32-vcmul/gen/f32-vcmul-scalar-u2.c &
diff --git a/src/configs/cmul-config.c b/src/configs/cmul-config.c
@@ -15,26 +15,24 @@
 #include "src/xnnpack/microfnptr.h"
 #include "src/xnnpack/vbinary.h"
 
-#if XNN_ENABLE_ARM_FP16_VECTOR && (XNN_ARCH_ARM || XNN_ARCH_ARM64)
-  static struct xnn_cmul_config f16_cmul_config = {0};
-#endif
+static struct xnn_cmul_config f16_cmul_config = {0};
 static struct xnn_cmul_config f32_cmul_config = {0};
 
-#if XNN_ENABLE_ARM_FP16_VECTOR && (XNN_ARCH_ARM || XNN_ARCH_ARM64)
-  XNN_INIT_ONCE_GUARD(f16_cmul);
-#endif
+XNN_INIT_ONCE_GUARD(f16_cmul);
 XNN_INIT_ONCE_GUARD(f32_cmul);
 
 // Macros to log the microkernel names if and when they are registered.
 #define XNN_INIT_CMUL_UKERNEL(ukernel) \
   (xnn_vbinary_ukernel_fn) ukernel;    \
   xnn_log_info("Using cmul microkernel '%s'.", #ukernel);
 
-#if XNN_ENABLE_ARM_FP16_VECTOR && (XNN_ARCH_ARM || XNN_ARCH_ARM64)
-  static void init_f16_cmul_config(void) {
-      f16_cmul_config.ukernel = XNN_INIT_CMUL_UKERNEL(xnn_f16_vcmul_ukernel__neonfp16arith_u16);
-  }
-#endif
+static void init_f16_cmul_config(void) {
+  #if XNN_ENABLE_ARM_FP16_VECTOR && (XNN_ARCH_ARM || XNN_ARCH_ARM64)
+    f16_cmul_config.ukernel = XNN_INIT_CMUL_UKERNEL(xnn_f16_vcmul_ukernel__neonfp16arith_u16);
+  #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_FP16_VECTOR
+    f16_cmul_config.ukernel = XNN_INIT_CMUL_UKERNEL(xnn_f16_vcmul_ukernel__rvvfp16arith_u2v);
+  #endif
+}
 
 static void init_f32_cmul_config(void) {
   #if XNN_ARCH_ARM
@@ -81,16 +79,12 @@ static void init_f32_cmul_config(void) {
 }
 
 const struct xnn_cmul_config* xnn_init_f16_cmul_config() {
-  #if XNN_ENABLE_ARM_FP16_VECTOR && (XNN_ARCH_ARM || XNN_ARCH_ARM64)
-    const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config();
-    if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) {
-      return NULL;
-    }
-    XNN_INIT_ONCE(f16_cmul);
-    return &f16_cmul_config;
-  #else
+  const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config();
+  if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) {
     return NULL;
-  #endif
+  }
+  XNN_INIT_ONCE(f16_cmul);
+  return f16_cmul_config.ukernel ? &f16_cmul_config : NULL;
 }
 
 const struct xnn_cmul_config* xnn_init_f32_cmul_config() {
diff --git a/src/f16-vbinary/f16-vcmul.inc b/src/f16-vbinary/f16-vcmul.inc
@@ -11,3 +11,8 @@ XNN_UKERNEL(xnn_arch_arm_neon_fp16_arith, xnn_f16_vcmul_ukernel__neonfp16arith_u
 XNN_UKERNEL(xnn_arch_arm_neon_fp16_arith, xnn_f16_vcmul_ukernel__neonfp16arith_u32, 32, false, xnn_float16, struct xnn_f16_default_params, ((xnn_init_f16_default_params_fn) NULL))
 #endif  // XNN_ENABLE_ARM_FP16_VECTOR && (XNN_ARCH_ARM || XNN_ARCH_ARM64)
 
+#if XNN_ARCH_RISCV && XNN_ENABLE_RISCV_FP16_VECTOR
+XNN_UKERNEL(xnn_arch_riscv_vector_fp16_arith, xnn_f16_vcmul_ukernel__rvvfp16arith_u1v, 1, true, float, struct xnn_f16_default_params, ((xnn_init_f16_default_params_fn) NULL))
+XNN_UKERNEL(xnn_arch_riscv_vector_fp16_arith, xnn_f16_vcmul_ukernel__rvvfp16arith_u2v, 2, true, float, struct xnn_f16_default_params, ((xnn_init_f16_default_params_fn) NULL))
+XNN_UKERNEL(xnn_arch_riscv_vector_fp16_arith, xnn_f16_vcmul_ukernel__rvvfp16arith_u4v, 4, true, float, struct xnn_f16_default_params, ((xnn_init_f16_default_params_fn) NULL))
+#endif  // XNN_ARCH_RISCV && XNN_ENABLE_RISCV_FP16_VECTOR
diff --git a/src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u1v.c b/src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u1v.c
@@ -0,0 +1,52 @@
+// clang-format off
+// Auto-generated file. Do not edit!
+//   Template: src/f16-vcmul/rvv.c.in
+//   Generator: tools/xngen
+//
+// Copyright 2026 Google LLC
+//
+// This source code is licensed under the BSD-style license found in the
+// LICENSE file in the root directory of this source tree.
+
+#include <assert.h>
+
+#include <riscv_vector.h>
+
+#include "src/xnnpack/vbinary.h"
+
+void xnn_f16_vcmul_ukernel__rvvfp16arith_u1v(
+    size_t batch,
+    const xnn_float16* input_a,
+    const xnn_float16* input_b,
+    xnn_float16* output,
+    const struct xnn_f16_default_params* restrict params)
+{
+  assert(batch != 0);
+  assert(batch % sizeof(xnn_float16) == 0);
+  assert(input_a != NULL);
+  assert(input_b != NULL);
+  assert(output != NULL);
+
+  batch >>= XNN_LOG2_SIZEOF_FLOAT16;
+
+  const xnn_float16* ar = input_a;
+  const xnn_float16* ai = input_a + batch;
+  const xnn_float16* br = input_b;
+  const xnn_float16* bi = input_b + batch;
+  xnn_float16* or = output;
+  xnn_float16* oi = output + batch;
+
+  do {
+    size_t n = __riscv_vsetvl_e16m1(batch); batch -= n;
+    vfloat16m1_t var = __riscv_vle16_v_f16m1(ar, n); ar += n;
+    vfloat16m1_t vai = __riscv_vle16_v_f16m1(ai, n); ai += n;
+    vfloat16m1_t vbr = __riscv_vle16_v_f16m1(br, n); br += n;
+    vfloat16m1_t vbi = __riscv_vle16_v_f16m1(bi, n); bi += n;
+    vfloat16m1_t vaccr = __riscv_vfmul(var, vbr, n);
+    vfloat16m1_t vacci = __riscv_vfmul(var, vbi, n);
+    vaccr = __riscv_vfnmsac(vaccr, vai, vbi, n);
+    vacci = __riscv_vfmacc(vacci, vai, vbr, n);
+    __riscv_vse16(or, vaccr, n); or += n;
+    __riscv_vse16(oi, vacci, n); oi += n;
+  } while (batch > 0);
+}
diff --git a/src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u2v.c b/src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u2v.c
@@ -0,0 +1,52 @@
+// clang-format off
+// Auto-generated file. Do not edit!
+//   Template: src/f16-vcmul/rvv.c.in
+//   Generator: tools/xngen
+//
+// Copyright 2026 Google LLC
+//
+// This source code is licensed under the BSD-style license found in the
+// LICENSE file in the root directory of this source tree.
+
+#include <assert.h>
+
+#include <riscv_vector.h>
+
+#include "src/xnnpack/vbinary.h"
+
+void xnn_f16_vcmul_ukernel__rvvfp16arith_u2v(
+    size_t batch,
+    const xnn_float16* input_a,
+    const xnn_float16* input_b,
+    xnn_float16* output,
+    const struct xnn_f16_default_params* restrict params)
+{
+  assert(batch != 0);
+  assert(batch % sizeof(xnn_float16) == 0);
+  assert(input_a != NULL);
+  assert(input_b != NULL);
+  assert(output != NULL);
+
+  batch >>= XNN_LOG2_SIZEOF_FLOAT16;
+
+  const xnn_float16* ar = input_a;
+  const xnn_float16* ai = input_a + batch;
+  const xnn_float16* br = input_b;
+  const xnn_float16* bi = input_b + batch;
+  xnn_float16* or = output;
+  xnn_float16* oi = output + batch;
+
+  do {
+    size_t n = __riscv_vsetvl_e16m2(batch); batch -= n;
+    vfloat16m2_t var = __riscv_vle16_v_f16m2(ar, n); ar += n;
+    vfloat16m2_t vai = __riscv_vle16_v_f16m2(ai, n); ai += n;
+    vfloat16m2_t vbr = __riscv_vle16_v_f16m2(br, n); br += n;
+    vfloat16m2_t vbi = __riscv_vle16_v_f16m2(bi, n); bi += n;
+    vfloat16m2_t vaccr = __riscv_vfmul(var, vbr, n);
+    vfloat16m2_t vacci = __riscv_vfmul(var, vbi, n);
+    vaccr = __riscv_vfnmsac(vaccr, vai, vbi, n);
+    vacci = __riscv_vfmacc(vacci, vai, vbr, n);
+    __riscv_vse16(or, vaccr, n); or += n;
+    __riscv_vse16(oi, vacci, n); oi += n;
+  } while (batch > 0);
+}
diff --git a/src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u4v.c b/src/f16-vcmul/gen/f16-vcmul-rvvfp16arith-u4v.c
@@ -0,0 +1,52 @@
+// clang-format off
+// Auto-generated file. Do not edit!
+//   Template: src/f16-vcmul/rvv.c.in
+//   Generator: tools/xngen
+//
+// Copyright 2026 Google LLC
+//
+// This source code is licensed under the BSD-style license found in the
+// LICENSE file in the root directory of this source tree.
+
+#include <assert.h>
+
+#include <riscv_vector.h>
+
+#include "src/xnnpack/vbinary.h"
+
+void xnn_f16_vcmul_ukernel__rvvfp16arith_u4v(
+    size_t batch,
+    const xnn_float16* input_a,
+    const xnn_float16* input_b,
+    xnn_float16* output,
+    const struct xnn_f16_default_params* restrict params)
+{
+  assert(batch != 0);
+  assert(batch % sizeof(xnn_float16) == 0);
+  assert(input_a != NULL);
+  assert(input_b != NULL);
+  assert(output != NULL);
+
+  batch >>= XNN_LOG2_SIZEOF_FLOAT16;
+
+  const xnn_float16* ar = input_a;
+  const xnn_float16* ai = input_a + batch;
+  const xnn_float16* br = input_b;
+  const xnn_float16* bi = input_b + batch;
+  xnn_float16* or = output;
+  xnn_float16* oi = output + batch;
+
+  do {
+    size_t n = __riscv_vsetvl_e16m4(batch); batch -= n;
+    vfloat16m4_t var = __riscv_vle16_v_f16m4(ar, n); ar += n;
+    vfloat16m4_t vai = __riscv_vle16_v_f16m4(ai, n); ai += n;
+    vfloat16m4_t vbr = __riscv_vle16_v_f16m4(br, n); br += n;
+    vfloat16m4_t vbi = __riscv_vle16_v_f16m4(bi, n); bi += n;
+    vfloat16m4_t vaccr = __riscv_vfmul(var, vbr, n);
+    vfloat16m4_t vacci = __riscv_vfmul(var, vbi, n);
+    vaccr = __riscv_vfnmsac(vaccr, vai, vbi, n);
+    vacci = __riscv_vfmacc(vacci, vai, vbr, n);
+    __riscv_vse16(or, vaccr, n); or += n;
+    __riscv_vse16(oi, vacci, n); oi += n;
+  } while (batch > 0);
+}
diff --git a/src/f16-vcmul/rvv.c.in b/src/f16-vcmul/rvv.c.in
