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| 1 | +[registers.ICC_SRE_EL2] |
| 2 | + |
| 3 | +[registers.SCR_EL3.field_descriptions] |
| 4 | +NS = "Non-secure." |
| 5 | +IRQ = "Take physical IRQs at EL3." |
| 6 | +FIQ = "Take physical FIQs at EL3." |
| 7 | +EA = "Take external abort and SError exceptions at EL3." |
| 8 | +SMD = "Disable SMC instructions." |
| 9 | +HCE = "Enable HVC instructions." |
| 10 | +SIF = "Disable execution from non-secure memory." |
| 11 | +RW = "Enable AArch64 in lower ELs." |
| 12 | +ST = "Trap physical secure timer to EL3." |
| 13 | +TWI = "Trap WFI to EL3." |
| 14 | +TWE = "Trap WFE to EL3." |
| 15 | +TLOR = "Trap LOR register access to EL3." |
| 16 | +TERR = "Trap error record register access to EL3." |
| 17 | +APK = "Don't trap PAC key registers to EL3." |
| 18 | +API = "Don't trap PAuth instructions to EL3." |
| 19 | +EEL2 = "Enable Secure EL2." |
| 20 | +EASE = "Synchronous external aborts are taken as SErrors." |
| 21 | +NMEA = "Take SError exceptions at EL3." |
| 22 | +FIEN = "Enable fault injection at lower ELs." |
| 23 | +TID3 = "Trap ID group 3 registers to EL3." |
| 24 | +TID5 = "Trap ID group 5 register to EL3." |
| 25 | +EnSCXT = "Enable SCXT at lower ELs." |
| 26 | +ATA = "Enable memory tagging at lower ELs." |
| 27 | +FGTEn = "Enable fine-grained traps to EL2." |
| 28 | +ECVEn = "Enable access to CNTPOFF_EL2." |
| 29 | +TWEDEn = "Enable a configurable delay for WFE traps." |
| 30 | +TME = "Enable access to TME at lower ELs." |
| 31 | +AMVOFFEN = "Enable acivity monitors virtual offsets." |
| 32 | +EnAS0 = "Enable ST64BV0 at lower ELs." |
| 33 | +ADEn = "Enable ACCDATA_EL1 at lower ELs." |
| 34 | +HXEn = "Enable HCRX_EL2." |
| 35 | +GCSEn = "Enable gaurded control stack." |
| 36 | +TRNDR = "Trap RNDR and RNDRRS to EL3." |
| 37 | +EnTP2 = "Enable TPIDR2_EL0 at lower ELs." |
| 38 | +RCWMASKEn = "Enable RCW and RCWS mask registers at lower ELs." |
| 39 | +TCR2En = "Enable TCR2_ELx registers at lower ELs." |
| 40 | +SCTLR2En = "Enable SCTLR2_ELx rogisters at lower ELs." |
| 41 | +PIEn = "Enable permission indirection and overlay registers at lower ELs." |
| 42 | +AIEn = "Enable MAIR2_ELx and AMAIR2_ELx at lower ELs." |
| 43 | +D128En = "Enable 128-bit system registers at lower ELs." |
| 44 | +GPF = "Route GPFs to EL3." |
| 45 | +MECEn = "Enable MECID registers at EL2." |
| 46 | +EnFPM = "Enable access to FPMR at lower ELs." |
| 47 | +TMEA = "Take synchronous external abort and physical SError exception to EL3." |
| 48 | +TWERR = "Trap writes to Error Record registers to EL3." |
| 49 | +PFAREn = "Enable access to physical fault address registers at lower ELs." |
| 50 | +SRMASKEn = "Enable access to mask registers at lower ELs." |
| 51 | +EnIDCP128 = "Enable implementation-defined 128-bit system registers." |
| 52 | +DSE = "A delegated SError exception is pending." |
| 53 | +EnDSE = "Enable delegated SError exceptions." |
| 54 | +FGTEn2 = "Enable fine-grained traps to EL2." |
| 55 | +HDBSSEn = "Enable HDBSSBR_EL2 and HDBSSPROD_EL2 registers at EL2." |
| 56 | +HACDBSEn = "Enable HACDBSBR_EL2 and HACDBSCONS_EL2 registers at EL2." |
| 57 | +NSE = "Non-secure realm world bit." |
| 58 | + |
| 59 | +[registers.CLIDR_EL1.field_descriptions] |
| 60 | +LoC = "Level of Coherence for the cache hierarchy." |
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