Formatted with hackrf clang 14 style

Author: fabriziop

firmware/common/clkin.c

@@ -73,9 +73,9 @@ void clkin_detect_init(void)
 
 	reset.first_tcr = TIMER_TCR_CEN | TIMER_TCR_CRST;
 	reset.second_tcr = TIMER_TCR_CEN;
-	timer_dma_lli.src = (uint32_t) & (reset);
-	timer_dma_lli.dest = (uint32_t) & (TIMER2_TCR);
-	timer_dma_lli.next_lli = (uint32_t) & (timer_dma_lli);
+	timer_dma_lli.src = (uint32_t) &(reset);
+	timer_dma_lli.dest = (uint32_t) &(TIMER2_TCR);
+	timer_dma_lli.next_lli = (uint32_t) &(timer_dma_lli);
 	timer_dma_lli.control = GPDMA_CCONTROL_TRANSFERSIZE(2) |
 		GPDMA_CCONTROL_SBSIZE(0)   // 1
 		| GPDMA_CCONTROL_DBSIZE(0) // 1

firmware/common/gpio_lpc.h

@@ -45,7 +45,7 @@ typedef struct gpio_port_t {
 	uint32_t _reserved4[31];
 	volatile uint32_t clr; /* +0x280 */
 	uint32_t _reserved5[31];
-	volatile uint32_t not ; /* +0x300 */
+	volatile uint32_t not; /* +0x300 */
 } gpio_port_t;
 
 struct gpio_t {
@@ -60,9 +60,10 @@ struct gpio_t {
 #define GPIO_LPC_PORT_OFFSET (0x2000)
 
 #define GPIO_LPC_PORT(_n) \
-	((gpio_port_t*) ((GPIO_LPC_BASE + GPIO_LPC_PORT_OFFSET) + (_n) *4))
-#define GPIO_LPC_W(_port_num, _pin_num) \
-	(volatile uint32_t*) ((GPIO_LPC_BASE + GPIO_LPC_W_OFFSET) + ((_port_num) *0x80) + ((_pin_num) *4))
+	((gpio_port_t*) ((GPIO_LPC_BASE + GPIO_LPC_PORT_OFFSET) + (_n) * 4))
+#define GPIO_LPC_W(_port_num, _pin_num)                             \
+	(volatile uint32_t*) ((GPIO_LPC_BASE + GPIO_LPC_W_OFFSET) + \
+			      ((_port_num) * 0x80) + ((_pin_num) * 4))
 
 // clang-format off
 #define GPIO(_port_num, _pin_num) { \

firmware/common/hackrf_core.c

@@ -540,7 +540,7 @@ Configure PLL1 (Main MCU Clock) to max speed (204MHz).
 Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
 This function shall be called after cpu_clock_init().
 */
-void cpu_clock_pll1_max_speed(uint8_t clock_source,uint8_t msel)
+void cpu_clock_pll1_max_speed(uint8_t clock_source, uint8_t msel)
 {
 	uint32_t reg_val;
 
@@ -606,7 +606,7 @@ void cpu_clock_pll1_max_speed(uint8_t clock_source,uint8_t msel)
 
 /* clock startup for LPC4320 configure PLL1 to max speed (204MHz).
 Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */
-void cpu_clock_init(uint8_t clock_source,uint8_t msel)
+void cpu_clock_init(uint8_t clock_source, uint8_t msel)
 {
 	/* use IRC as clock source for APB1 (including I2C0) */
 	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
@@ -696,7 +696,7 @@ void cpu_clock_init(uint8_t clock_source,uint8_t msel)
 	/* set xtal oscillator to low frequency mode */
 	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;
 
-	cpu_clock_pll1_max_speed(clock_source,msel);
+	cpu_clock_pll1_max_speed(clock_source, msel);
 
 	/* use XTAL_OSC as clock source for APB1 */
 	CGU_BASE_APB1_CLK =
@@ -881,10 +881,10 @@ void pin_setup(void)
 	 * LPC43xx pull-up and pull-down resistors are approximately 53K.
 	 */
 
-        /* configure pin as TIMER 3 MATCH 0 output: 1pps out */
-        scu_pinmux(SCU_PINMUX_PPS1, SCU_GPIO_PDN | SCU_CONF_FUNCTION6);
-        /* configure pin as TIMER 3 MATCH 1 output: sampling trigger out */
-        scu_pinmux(SCU_PINMUX_SAMP_TRIGGER, SCU_GPIO_PDN | SCU_CONF_FUNCTION6);
+	/* configure pin as TIMER 3 MATCH 0 output: 1pps out */
+	scu_pinmux(SCU_PINMUX_PPS1, SCU_GPIO_PDN | SCU_CONF_FUNCTION6);
+	/* configure pin as TIMER 3 MATCH 1 output: sampling trigger out */
+	scu_pinmux(SCU_PINMUX_SAMP_TRIGGER, SCU_GPIO_PDN | SCU_CONF_FUNCTION6);
 
 #ifdef HACKRF_ONE
 	scu_pinmux(SCU_PINMUX_PP_TMS, SCU_GPIO_PUP | SCU_CONF_FUNCTION0);
@@ -976,7 +976,6 @@ void pin_setup(void)
 	else
 		scu_pinmux(SCU_PINMUX_GP_CLKIN_NOTR9, SCU_CLK_IN | SCU_CONF_FUNCTION1);
 
-
 	sgpio_configure_pin_functions(&sgpio_config);
 }
 

firmware/common/hackrf_core.h

@@ -65,11 +65,11 @@ extern "C" {
 	#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */
 #endif
 
-#define SCU_PINMUX_PP_LCD_TE  (P2_3)  /* GPIO5[3] on P2_3 */
-#define SCU_PINMUX_PPS1  (P2_3)  /* T3_MAT0 on P2_3, cpu pin 87 */
+#define SCU_PINMUX_PP_LCD_TE (P2_3) /* GPIO5[3] on P2_3 */
+#define SCU_PINMUX_PPS1      (P2_3) /* T3_MAT0 on P2_3, cpu pin 87 */
 
-#define SCU_PINMUX_PP_LCD_RDX (P2_4)  /* GPIO5[4] on P2_4 */
-#define SCU_PINMUX_SAMP_TRIGGER (P2_4)  /* T3_MAT1 on P2_4, cpu pin 88 */
+#define SCU_PINMUX_PP_LCD_RDX   (P2_4) /* GPIO5[4] on P2_4 */
+#define SCU_PINMUX_SAMP_TRIGGER (P2_4) /* T3_MAT1 on P2_4, cpu pin 88 */
 
 #define SCU_PINMUX_PP_UNUSED  (P2_8)  /* GPIO5[7] on P2_8 */
 #define SCU_PINMUX_PP_LCD_WRX (P2_9)  /* GPIO1[10] on P2_9 */
@@ -236,7 +236,7 @@ extern "C" {
 
 #define SCU_PINMUX_ISP (P2_7) /* GPIO0[7] */
 
-#define SCU_PINMUX_GP_CLKIN_R9 (P4_7)
+#define SCU_PINMUX_GP_CLKIN_R9    (P4_7)
 #define SCU_PINMUX_GP_CLKIN_NOTR9 (PF_4)
 
 /* HackRF One r9 */
@@ -323,7 +323,7 @@ void hw_sync_enable(const hw_sync_mode_t hw_sync_mode);
 
 void halt_and_flash(const uint32_t duration);
 
-void cpu_clock_pll1_max_speed(uint8_t clock_source,uint8_t msel);
+void cpu_clock_pll1_max_speed(uint8_t clock_source, uint8_t msel);
 
 #ifdef __cplusplus
 }

firmware/common/rad1o/render.c

@@ -108,7 +108,7 @@ int rad1o_DoChar(int sx, int sy, int c)
 
 	} while (0);
 
-#define xy_(x, y) ((x < 0 || y < 0 || x >= RESX || y >= RESY) ? 0 : (y) *RESX + (x))
+#define xy_(x, y) ((x < 0 || y < 0 || x >= RESX || y >= RESY) ? 0 : (y) * RESX + (x))
 #define gPx(x, y) (data[x * height + (height - y / 8 - 1)] & (1 << (y % 8)))
 
 	int x = 0;

firmware/common/rom_iap.c

@@ -36,7 +36,7 @@ typedef void (*IAP_t)(uint32_t[], uint32_t[]);
 typedef struct {
 	const IAP_t IAP; /* If equal to 0x12345678 IAP not implemented */
 			 /* Other TBD */
-} * pENTRY_ROM_API_t;
+}* pENTRY_ROM_API_t;
 
 #define pROM_API ((pENTRY_ROM_API_t) ROM_IAP_ADDR)
 

firmware/common/sct.h

@@ -2310,7 +2310,7 @@ EV[0:15]_CTRL[MATCHMEM, DIRECTION]
 /* -- SCT_OUTn_SETm: A 1 in bit m selects event m to set output n (or clear it
  * if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 =
  * bit 15. */
-#define SCT_OUTn_SETm(n, m) (((n) &1) << (m))
+#define SCT_OUTn_SETm(n, m) (((n) & 1) << (m))
 
 /* --- SCT_OUT0_CLR -------------------------------------- */
 #define SCT_OUT0_CLR MMIO32(SCT_BASE + 0x504)
@@ -2363,4 +2363,4 @@ EV[0:15]_CTRL[MATCHMEM, DIRECTION]
 /* -- SCT_OUTn_CLR_CLRm: A 1 in bit m selects event m to clear output n (or set
  * it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 =
  * bit 15. */
-#define SCT_OUTn_CLRm(n, m) (((n) &1) << (m))
+#define SCT_OUTn_CLRm(n, m) (((n) & 1) << (m))

firmware/common/si5351c.c

@@ -229,21 +229,19 @@ void si5351c_configure_clock_control(
 
 		if (mcu_clk_sync && detected_platform() != BOARD_ID_HACKRF1_R9) {
 			clkout_ctrl |= SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4);
-			si5351c_configure_multisynth(drv,3,80 * 128 - 512,0,0,1);
-		}
-		else {
+			si5351c_configure_multisynth(drv, 3, 80 * 128 - 512, 0, 0, 1);
+		} else {
 			clkout_ctrl |= SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF);
 		}
-	}
-	else {
+	} else {
 		clkout_ctrl = SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE;
 	}
 
 	/* Clock to CPU is deactivated as it is not used and creates noise */
 	/* External clock output is kept in current state */
 	uint8_t data[] = {
 		16,
-								SI5351C_CLK_PLL_SRC(pll) |
+		SI5351C_CLK_PLL_SRC(pll) |
 			SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
 			SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA),
 		SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) |
@@ -266,16 +264,15 @@ void si5351c_configure_clock_control(
 	if (mcu_clk_sync) {
 		data[1] |= SI5351C_CLK_INT_MODE;
 		data[6] |= SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4);
-	}
-	else {
+	} else {
 		data[1] |= SI5351C_CLK_FRAC_MODE;
 		data[6] |= SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF);
 	}
 	if (detected_platform() == BOARD_ID_HACKRF1_R9) {
 		data[1] = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC_A |
 			SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
 			SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA);
-		data[2] = 						SI5351C_CLK_PLL_SRC_A |
+		data[2] = SI5351C_CLK_PLL_SRC_A |
 			SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
 			SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA);
 		data[3] = clkout_ctrl;
@@ -409,8 +406,7 @@ void si5351c_mcu_clk_sync(si5351c_driver_t* const drv, uint8_t enable)
 {
 	mcu_clk_sync = (enable > 0);
 
-	si5351c_clkout_enable(drv,enable);
-
+	si5351c_clkout_enable(drv, enable);
 }
 
 void si5351c_init(si5351c_driver_t* const drv)

firmware/common/si5351c.h

@@ -104,7 +104,7 @@ void si5351c_write(
 	const size_t data_count);
 void si5351c_clkout_enable(si5351c_driver_t* const drv, uint8_t enable);
 void si5351c_mcu_clk_enable(uint8_t enable);
-void si5351c_mcu_clk_sync(si5351c_driver_t* const drv,uint8_t enable);
+void si5351c_mcu_clk_sync(si5351c_driver_t* const drv, uint8_t enable);
 void si5351c_init(si5351c_driver_t* const drv);
 
 #ifdef __cplusplus

firmware/common/ui_rad1o.c

@@ -272,8 +272,8 @@ static void rad1o_ui_set_bb_tx_vga_gain(const uint32_t gain_db)
 	ui_update();
 }
 
-static void rad1o_ui_set_first_if_frequency(const uint64_t frequency
-					    __attribute__((unused)))
+static void rad1o_ui_set_first_if_frequency(
+	const uint64_t frequency __attribute__((unused)))
 {
 	// Not implemented
 }