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antoinevgantoinevg
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firmware: remove remaining scu and gpio declarations
1 parent fefd0ab commit 40b52af

6 files changed

Lines changed: 67 additions & 135 deletions

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‎firmware/common/cpld_jtag.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -28,15 +28,15 @@
2828

2929
typedef struct jtag_gpio_t {
3030
gpio_t gpio_tck;
31-
#ifndef PRALINE
31+
//#ifndef PRALINE
3232
gpio_t gpio_tms;
3333
gpio_t gpio_tdi;
3434
gpio_t gpio_tdo;
35-
#endif
36-
#if (defined HACKRF_ONE || defined PRALINE)
35+
//#endif
36+
//#if (defined HACKRF_ONE || defined PRALINE)
3737
gpio_t gpio_pp_tms;
3838
gpio_t gpio_pp_tdo;
39-
#endif
39+
//#endif
4040
} jtag_gpio_t;
4141

4242
typedef struct jtag_t {

‎firmware/common/hackrf_core.c‎

Lines changed: 58 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -79,47 +79,21 @@ si5351c_driver_t clock_gen = {
7979
.i2c_address = 0x60,
8080
};
8181

82-
spi_bus_t spi_bus_ssp1 = {
83-
.obj = (void*) SSP1_BASE,
84-
.config = &ssp_config_max5864,
85-
.start = spi_ssp_start,
86-
.stop = spi_ssp_stop,
87-
.transfer = spi_ssp_transfer,
88-
.transfer_gather = spi_ssp_transfer_gather,
89-
};
90-
91-
#ifdef PRALINE
92-
const ssp_config_t ssp_config_max283x = {
93-
/* FIXME speed up once everything is working reliably */
94-
/*
95-
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
96-
const uint8_t serial_clock_rate = 32;
97-
const uint8_t clock_prescale_rate = 128;
98-
*/
99-
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
100-
.data_bits = SSP_DATA_9BITS, // send 2 words
101-
.serial_clock_rate = 21,
102-
.clock_prescale_rate = 2,
103-
.gpio_select = &gpio_max283x_select,
104-
};
105-
#else
106-
const ssp_config_t ssp_config_max283x = {
82+
static ssp_config_t ssp_config_max283x = {
10783
/* FIXME speed up once everything is working reliably */
10884
/*
10985
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
11086
const uint8_t serial_clock_rate = 32;
11187
const uint8_t clock_prescale_rate = 128;
11288
*/
11389
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
114-
.data_bits = SSP_DATA_16BITS,
11590
.serial_clock_rate = 21,
11691
.clock_prescale_rate = 2,
117-
.gpio_select = &gpio_max283x_select,
11892
};
119-
#endif
93+
12094
max283x_driver_t max283x = {};
12195

122-
const ssp_config_t ssp_config_max5864 = {
96+
static ssp_config_t ssp_config_max5864 = {
12397
/* FIXME speed up once everything is working reliably */
12498
/*
12599
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
@@ -130,22 +104,29 @@ const ssp_config_t ssp_config_max5864 = {
130104
.data_bits = SSP_DATA_8BITS,
131105
.serial_clock_rate = 21,
132106
.clock_prescale_rate = 2,
133-
.gpio_select = &gpio_max5864_select,
107+
};
108+
109+
spi_bus_t spi_bus_ssp1 = {
110+
.obj = (void*) SSP1_BASE,
111+
.config = &ssp_config_max5864,
112+
.start = spi_ssp_start,
113+
.stop = spi_ssp_stop,
114+
.transfer = spi_ssp_transfer,
115+
.transfer_gather = spi_ssp_transfer_gather,
134116
};
135117

136118
max5864_driver_t max5864 = {
137119
.bus = &spi_bus_ssp1,
138120
.target_init = max5864_target_init,
139121
};
140122

141-
const ssp_config_t ssp_config_w25q80bv = {
123+
ssp_config_t ssp_config_w25q80bv = {
142124
.data_bits = SSP_DATA_8BITS,
143125
.serial_clock_rate = 2,
144126
.clock_prescale_rate = 2,
145-
.gpio_select = &gpio_w25q80bv_select,
146127
};
147128

148-
spi_bus_t spi_bus_ssp0 = {
129+
static spi_bus_t spi_bus_ssp0 = {
149130
.obj = (void*) SSP0_BASE,
150131
.config = &ssp_config_w25q80bv,
151132
.start = spi_ssp_start,
@@ -156,39 +137,27 @@ spi_bus_t spi_bus_ssp0 = {
156137

157138
w25q80bv_driver_t spi_flash = {
158139
.bus = &spi_bus_ssp0,
159-
.gpio_hold = &gpio_w25q80bv_hold,
160-
.gpio_wp = &gpio_w25q80bv_wp,
161140
.target_init = w25q80bv_target_init,
162141
};
163142

164143
sgpio_config_t sgpio_config = {
165-
.gpio_q_invert = &gpio_q_invert,
166-
#ifndef PRALINE
167-
.gpio_trigger_enable = &gpio_trigger_enable,
168-
#endif
169144
.slice_mode_multislice = true,
170145
};
171146

172-
#ifdef PRALINE
173-
const ssp_config_t ssp_config_ice40_fpga = {
147+
static ssp_config_t ssp_config_ice40_fpga = {
174148
.data_bits = SSP_DATA_8BITS,
175149
.spi_mode = SSP_CPOL_1_CPHA_1,
176150
.serial_clock_rate = 21,
177151
.clock_prescale_rate = 2,
178-
.gpio_select = &gpio_fpga_cfg_spi_cs,
179152
};
180153

181154
ice40_spi_driver_t ice40 = {
182155
.bus = &spi_bus_ssp1,
183-
.gpio_select = &gpio_fpga_cfg_spi_cs,
184-
.gpio_creset = &gpio_fpga_cfg_creset,
185-
.gpio_cdone = &gpio_fpga_cfg_cdone,
186156
};
187157

188158
fpga_driver_t fpga = {
189159
.bus = &ice40,
190160
};
191-
#endif
192161

193162
radio_t radio = {
194163
.channel[RADIO_CHANNEL0] =
@@ -228,18 +197,7 @@ radio_t radio = {
228197
// rf_path gpio's now get assigned in pin_setup() TODO delete comment
229198
rf_path_t rf_path;
230199

231-
jtag_gpio_t jtag_gpio_cpld = {
232-
.gpio_tck = &gpio_cpld_tck,
233-
#ifndef PRALINE
234-
.gpio_tms = &gpio_cpld_tms,
235-
.gpio_tdi = &gpio_cpld_tdi,
236-
.gpio_tdo = &gpio_cpld_tdo,
237-
#endif
238-
#if (defined HACKRF_ONE || defined PRALINE)
239-
.gpio_pp_tms = &gpio_cpld_pp_tms,
240-
.gpio_pp_tdo = &gpio_cpld_pp_tdo,
241-
#endif
242-
};
200+
jtag_gpio_t jtag_gpio_cpld;
243201

244202
jtag_t jtag_cpld = {
245203
.gpio = &jtag_gpio_cpld,
@@ -1007,6 +965,7 @@ void pin_setup(void)
1007965
const platform_gpio_t* gpio = platform_gpio();
1008966
const platform_scu_t* scu = platform_scu();
1009967

968+
/* Configure LEDs */
1010969
led_off(0);
1011970
led_off(1);
1012971
led_off(2);
@@ -1030,6 +989,47 @@ void pin_setup(void)
1030989
break;
1031990
}
1032991

992+
/* Configure drivers and driver pins */
993+
ssp_config_max283x.gpio_select = gpio->max283x_select;
994+
if (board_id == BOARD_ID_PRALINE) {
995+
ssp_config_max283x.data_bits = SSP_DATA_9BITS; // send 2 words
996+
} else {
997+
ssp_config_max283x.data_bits = SSP_DATA_16BITS;
998+
}
999+
1000+
ssp_config_max5864.gpio_select = gpio->max5864_select;
1001+
1002+
ssp_config_w25q80bv.gpio_select = gpio->w25q80bv_select;
1003+
spi_flash.gpio_hold = gpio->w25q80bv_hold;
1004+
spi_flash.gpio_wp = gpio->w25q80bv_wp;
1005+
1006+
sgpio_config.gpio_q_invert = gpio->q_invert;
1007+
if (board_id != BOARD_ID_PRALINE) {
1008+
sgpio_config.gpio_trigger_enable = gpio->trigger_enable;
1009+
}
1010+
1011+
ssp_config_ice40_fpga.gpio_select = gpio->fpga_cfg_spi_cs;
1012+
ice40.gpio_select = gpio->fpga_cfg_spi_cs;
1013+
ice40.gpio_creset = gpio->fpga_cfg_creset;
1014+
ice40.gpio_cdone = gpio->fpga_cfg_cdone;
1015+
1016+
jtag_gpio_cpld.gpio_tck = gpio->cpld_tck;
1017+
if (board_id != BOARD_ID_PRALINE) {
1018+
jtag_gpio_cpld.gpio_tms = gpio->cpld_tms;
1019+
jtag_gpio_cpld.gpio_tdi = gpio->cpld_tdi;
1020+
jtag_gpio_cpld.gpio_tdo = gpio->cpld_tdo;
1021+
}
1022+
switch (board_id) {
1023+
case BOARD_ID_HACKRF1_OG:
1024+
case BOARD_ID_HACKRF1_R9:
1025+
case BOARD_ID_PRALINE:
1026+
jtag_gpio_cpld.gpio_pp_tms = gpio->cpld_pp_tms;
1027+
jtag_gpio_cpld.gpio_pp_tdo = gpio->cpld_pp_tdo;
1028+
break;
1029+
default:
1030+
break;
1031+
}
1032+
10331033
ssp1_set_mode_max283x();
10341034

10351035
mixer_bus_setup(&mixer);

‎firmware/common/hackrf_core.h‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -50,9 +50,7 @@ void delay_us_at_mhz(uint32_t us, uint32_t mhz);
5050

5151
/* TODO: Hide these configurations */
5252
extern si5351c_driver_t clock_gen;
53-
extern const ssp_config_t ssp_config_w25q80bv;
54-
extern const ssp_config_t ssp_config_max283x;
55-
extern const ssp_config_t ssp_config_max5864;
53+
extern ssp_config_t ssp_config_w25q80bv;
5654

5755
extern max283x_driver_t max283x;
5856
#ifdef PRALINE
@@ -74,7 +72,6 @@ void clock_gen_shutdown(void);
7472
void ssp1_set_mode_max283x(void);
7573
void ssp1_set_mode_max5864(void);
7674
#ifdef PRALINE
77-
void ssp1_set_mode_max2831(void);
7875
void ssp1_set_mode_ice40(void);
7976
#endif
8077

‎firmware/common/platform_gpio.h‎

Lines changed: 0 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -130,7 +130,6 @@ const platform_gpio_t* platform_gpio();
130130

131131
/* LPC43xx GPIO pre-declarations - we use these instead of the GPIO()
132132
macro so that we can assign them at runtime. */
133-
134133
static const struct gpio_t GPIO0_0 = GPIO(0, 0);
135134
static const struct gpio_t GPIO0_1 = GPIO(0, 1);
136135
static const struct gpio_t GPIO0_2 = GPIO(0, 2);
@@ -303,60 +302,6 @@ static const struct gpio_t GPIO7_23 = GPIO(7, 23);
303302
static const struct gpio_t GPIO7_24 = GPIO(7, 24);
304303
static const struct gpio_t GPIO7_25 = GPIO(7, 25);
305304

306-
// - old ------------------------------------------------------------------
307-
308-
// clang-format off
309-
310-
/* MAX283x GPIO (XCVR_CTL / CS_XCVR) PinMux */
311-
#ifdef PRALINE
312-
static struct gpio_t gpio_max283x_select = GPIO(6, 28);
313-
#else
314-
static struct gpio_t gpio_max283x_select = GPIO(0, 15);
315-
#endif
316-
317-
/* MAX5864 SPI chip select (AD_CS / CS_AD) GPIO PinMux */
318-
#ifdef PRALINE
319-
static struct gpio_t gpio_max5864_select = GPIO(6, 30);
320-
#else
321-
static struct gpio_t gpio_max5864_select = GPIO(2, 7);
322-
#endif
323-
324-
static struct gpio_t gpio_w25q80bv_hold = GPIO(1, 14);
325-
static struct gpio_t gpio_w25q80bv_wp = GPIO(1, 15);
326-
static struct gpio_t gpio_w25q80bv_select = GPIO(5, 11);
327-
328-
/* RF switch control - DONE */
329-
330-
/* CPLD JTAG interface GPIO pins, FPGA config pins in Praline */
331-
static struct gpio_t gpio_cpld_tck = GPIO(3, 0);
332-
#ifdef PRALINE
333-
static struct gpio_t gpio_fpga_cfg_creset = GPIO(2, 11);
334-
static struct gpio_t gpio_fpga_cfg_cdone = GPIO(5, 14);
335-
static struct gpio_t gpio_fpga_cfg_spi_cs = GPIO(2, 10);
336-
#else
337-
static struct gpio_t gpio_cpld_tdo = GPIO(5, 18);
338-
#if (defined HACKRF_ONE || defined RAD1O)
339-
static struct gpio_t gpio_cpld_tms = GPIO(3, 4);
340-
static struct gpio_t gpio_cpld_tdi = GPIO(3, 1);
341-
#else
342-
static struct gpio_t gpio_cpld_tms = GPIO(3, 1);
343-
static struct gpio_t gpio_cpld_tdi = GPIO(3, 4);
344-
#endif
345-
#endif
346-
347-
#if (defined HACKRF_ONE || defined PRALINE)
348-
static struct gpio_t gpio_cpld_pp_tms = GPIO(1, 1);
349-
static struct gpio_t gpio_cpld_pp_tdo = GPIO(1, 8);
350-
#endif
351-
352-
/* other CPLD interface GPIO pins */
353-
#ifndef PRALINE
354-
static struct gpio_t gpio_trigger_enable = GPIO(5, 12);
355-
#endif
356-
static struct gpio_t gpio_q_invert = GPIO(0, 13);
357-
358-
// clang-format on
359-
360305
#ifdef __cplusplus
361306
}
362307
#endif

‎firmware/common/platform_scu.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -35,9 +35,9 @@ const platform_scu_t* platform_scu()
3535
static platform_scu_t scu;
3636

3737
/* GPIO Output PinMux */
38-
scu.PINMUX_LED1 = (P4_1); /* GPIO2[1] on P4_1 */
39-
scu.PINMUX_LED2 = (P4_2); /* GPIO2[2] on P4_2 */
40-
scu.PINMUX_LED3 = (P6_12); /* GPIO2[8] on P6_12 */
38+
scu.PINMUX_LED1 = SCU_PINMUX_LED1; /* GPIO2[1] on P4_1 */
39+
scu.PINMUX_LED2 = SCU_PINMUX_LED2; /* GPIO2[2] on P4_2 */
40+
scu.PINMUX_LED3 = SCU_PINMUX_LED3; /* GPIO2[8] on P6_12 */
4141
switch (board_id) {
4242
case BOARD_ID_RAD1O:
4343
scu.PINMUX_LED4 = (PB_6); /* GPIO5[26] on PB_6 */

‎firmware/common/platform_scu.h‎

Lines changed: 1 addition & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,7 @@ extern "C" {
2727
#endif
2828

2929
#include <stddef.h>
30-
3130
#include <libopencm3/lpc43xx/scu.h>
32-
3331
#include "platform_detect.h"
3432

3533
/*
@@ -270,18 +268,10 @@ typedef struct {
270268
// Detects and returns the global platform scu instance of the active board id and revision.
271269
const platform_scu_t* platform_scu();
272270

273-
// - old ------------------------------------------------------------------
274-
275-
// TODO platform_detect needs these so we can't detect platform
271+
// Platform_detect needs these for error indication
276272
#define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */
277273
#define SCU_PINMUX_LED2 (P4_2) /* GPIO2[2] on P4_2 */
278274
#define SCU_PINMUX_LED3 (P6_12) /* GPIO2[8] on P6_12 */
279-
#ifdef RAD1O
280-
#define SCU_PINMUX_LED4 (PB_6) /* GPIO5[26] on PB_6 */
281-
#endif
282-
#ifdef PRALINE
283-
#define SCU_PINMUX_LED4 (P8_6) /* GPIO4[6] on P8_6 */
284-
#endif
285275

286276
#ifdef __cplusplus
287277
}

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