@@ -1343,13 +1343,13 @@ void DynaRecCPU::testSoftwareInterrupt() {
13431343 if constexpr (loadSR) {
13441344 gen.mov (eax, dword[contextPointer + COP0_OFFSET (12 )]); // eax = SR
13451345 }
1346- gen.test (eax, 1 ); // Check if interrupts are enabled
1347- gen.jz (label, CodeGenerator::LabelType:: T_NEAR ); // If not, skip to the end
1346+ gen.test (eax, 1 ); // Check if interrupts are enabled
1347+ gen.jz (label); // If not, skip to the end
13481348
13491349 gen.mov (arg2, dword[contextPointer + COP0_OFFSET (13 )]); // arg2 = CAUSE
13501350 gen.and_ (eax, arg2);
1351- gen.test (eax, 0x300 ); // Check if an interrupt was force-fired
1352- gen.jz (label, CodeGenerator::LabelType:: T_NEAR ); // Skip to the end if not
1351+ gen.test (eax, 0x300 ); // Check if an interrupt was force-fired
1352+ gen.jz (label); // Skip to the end if not
13531353
13541354 // Fire the interrupt if it was triggered
13551355 // This object in arg1. Exception code is already in arg2 from before (will be masked by exception handler)
@@ -1602,7 +1602,6 @@ void DynaRecCPU::recBLEZ() {
16021602 gen.mov (dword[contextPointer + PC_OFFSET ], eax);
16031603}
16041604
1605- // TODO: Handle INT_MIN / -1
16061605void DynaRecCPU::recDIV () {
16071606 Label notIntMin, divisionByZero, end;
16081607 bool emitIntMinCheck = true ;
@@ -1655,9 +1654,9 @@ void DynaRecCPU::recDIV() {
16551654 gen.mov (eax, m_regs[_Rs_].allocatedReg ); // Dividend in eax
16561655 }
16571656
1658- gen.mov (ecx, m_regs[_Rt_].allocatedReg ); // Divisor in ecx
1659- gen.test (ecx, ecx); // Check if divisor is 0
1660- gen.jz (divisionByZero, CodeGenerator::LabelType:: T_NEAR ); // Jump to divisionByZero label if so
1657+ gen.mov (ecx, m_regs[_Rt_].allocatedReg ); // Divisor in ecx
1658+ gen.test (ecx, ecx); // Check if divisor is 0
1659+ gen.jz (divisionByZero); // Jump to divisionByZero label if so
16611660 }
16621661
16631662 if (emitIntMinCheck) {
@@ -1677,8 +1676,8 @@ void DynaRecCPU::recDIV() {
16771676 gen.idiv (ecx); // Signed division by divisor
16781677
16791678 if (!m_regs[_Rt_].isConst ()) { // Emit a division by 0 handler if the divisor is unknown at compile time
1680- gen.jmp (end, CodeGenerator::LabelType:: T_NEAR ); // skip to the end if not a div by zero
1681- gen.L (divisionByZero); // Here starts our division by 0 handler
1679+ gen.jmp (end); // skip to the end if not a div by zero
1680+ gen.L (divisionByZero); // Here starts our division by 0 handler
16821681
16831682 gen.mov (edx, eax); // Set hi to $rs
16841683 gen.shr (eax, 31 );
@@ -1730,18 +1729,18 @@ void DynaRecCPU::recDIVU() {
17301729 gen.mov (eax, m_regs[_Rs_].allocatedReg ); // Dividend in eax
17311730 }
17321731
1733- gen.mov (ecx, m_regs[_Rt_].allocatedReg ); // Divisor in ecx
1734- gen.test (ecx, ecx); // Check if divisor is 0
1735- gen.jz (divisionByZero, CodeGenerator::LabelType:: T_NEAR ); // Jump to divisionByZero label if so
1732+ gen.mov (ecx, m_regs[_Rt_].allocatedReg ); // Divisor in ecx
1733+ gen.test (ecx, ecx); // Check if divisor is 0
1734+ gen.jz (divisionByZero); // Jump to divisionByZero label if so
17361735 }
17371736
1738- gen.xor_ (edx, edx); // Set top 32 bits of dividend to
1737+ gen.xor_ (edx, edx); // Set top 32 bits of dividend to 0
17391738 gen.div (ecx); // Unsigned division by divisor
17401739
17411740 if (!m_regs[_Rt_].isConst ()) { // Emit a division by 0 handler if the divisor is unknown at compile time
17421741 Label end;
1743- gen.jmp (end, CodeGenerator::LabelType:: T_NEAR ); // skip to the end if not a div by zero
1744- gen.L (divisionByZero); // Here starts our division by 0 handler
1742+ gen.jmp (end); // skip to the end if not a div by zero
1743+ gen.L (divisionByZero); // Here starts our division by 0 handler
17451744
17461745 gen.mov (edx, eax); // Set hi to $rs
17471746 gen.mov (eax, -1 ); // Set lo to -1
0 commit comments