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Fix timer update to process chained events and adjust test targets
The update() loop used 'if' to check each counter, processing at most one event per call. When a counter passed both target and overflow between updates, only the target event was handled - the overflow flag was never set until a subsequent update. Change to 'while' so chained events are fully drained. Also bump the hit-target-flag test target from 0x0010 to 0x1000 so the counter doesn't re-hit target between two back-to-back mode reads. Signed-off-by: Nicolas 'Pixel' Noble <nicolas@nobis-crew.org>
1 parent 76df40a commit a639859

2 files changed

Lines changed: 8 additions & 8 deletions

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src/core/psxcounters.cc

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -171,17 +171,17 @@ void PCSX::Counters::update() {
171171
}
172172

173173
// rcnt 0.
174-
if (cycle - m_rcnts[0].cycleStart >= m_rcnts[0].cycle) {
174+
while (cycle - m_rcnts[0].cycleStart >= m_rcnts[0].cycle) {
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reset(0);
176176
}
177177

178178
// rcnt 1.
179-
if (cycle - m_rcnts[1].cycleStart >= m_rcnts[1].cycle) {
179+
while (cycle - m_rcnts[1].cycleStart >= m_rcnts[1].cycle) {
180180
reset(1);
181181
}
182182

183183
// rcnt 2.
184-
if (cycle - m_rcnts[2].cycleStart >= m_rcnts[2].cycle) {
184+
while (cycle - m_rcnts[2].cycleStart >= m_rcnts[2].cycle) {
185185
reset(2);
186186
}
187187
// rcnt base.

src/mips/tests/timers/timers.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ static void waitVSync(void) {
7878
* The hit-target flag (bit 11) should be set after target is reached.
7979
* ================================================================= */
8080
CESTER_TEST(timerTargetResetHitsTarget, timer_tests,
81-
COUNTERS[2].target = 0x0010;
81+
COUNTERS[2].target = 0x1000;
8282
COUNTERS[2].mode = TM_RESET_TARGET;
8383
BUSY_WAIT(500);
8484

@@ -90,7 +90,7 @@ CESTER_TEST(timerTargetResetHitsTarget, timer_tests,
9090
/* Counter with reset-on-target should not overflow (bit 12 stays clear)
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* if target is well below 0xFFFF. */
9292
CESTER_TEST(timerTargetResetNoOverflow, timer_tests,
93-
COUNTERS[2].target = 0x0010;
93+
COUNTERS[2].target = 0x1000;
9494
COUNTERS[2].mode = TM_RESET_TARGET;
9595
BUSY_WAIT(500);
9696

@@ -159,15 +159,15 @@ CESTER_TEST(timerModeWriteResetsCounter, timer_tests,
159159
* ================================================================= */
160160
CESTER_TEST(timerHitTargetFlagSetAndCleared, timer_tests,
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/* Warmup pass to prime icache */
162-
COUNTERS[2].target = 0x0010;
162+
COUNTERS[2].target = 0x1000;
163163
COUNTERS[2].mode = TM_RESET_TARGET;
164-
BUSY_WAIT(500);
164+
BUSY_WAIT(50000);
165165
(void)COUNTERS[2].mode;
166166
(void)COUNTERS[2].mode;
167167

168168
/* Real measurement */
169169
COUNTERS[2].mode = TM_RESET_TARGET;
170-
BUSY_WAIT(500);
170+
BUSY_WAIT(50000);
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172172
uint16_t mode1 = COUNTERS[2].mode;
173173
uint16_t mode2 = COUNTERS[2].mode;

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