Timing measurements

Reset timing measurements

• Time from !RESET going low to address bus asserted to 0: 71.32us

• Time from !RESET going low to RD asserted to 0 for the first time: 72.55us

• Time between address bus asserted to 0 and RD asserted to 0 the first time: 1.23us

• Time between RD going low and BIOS chip emitting the proper byte out: 40ns

• Time between two BIOS reads at boot time: ~550ns

• Time between two BIOS or PIO reads after bus timings being set: ~175ns

Default PIO timings

The default bus timing settings is 3 cycles for Reads, and 15 cycles for Writes.

Bus timings 0:

• ~25ns RD and WR strobe time
• ~60ns CS strobe time

Bus timings 1:

• ~50ns RD and WR strobe time
• ~85ns CS strobe time

Bus timings 2:

• ~75ns RD and WR strobe time
• ~110ns CS strobe time