@@ -1093,7 +1093,6 @@ enum {
10931093 SNBEP_PCI_QPI_PORT0_FILTER ,
10941094 SNBEP_PCI_QPI_PORT1_FILTER ,
10951095 BDX_PCI_QPI_PORT2_FILTER ,
1096- HSWEP_PCI_PCU_3 ,
10971096};
10981097
10991098static int snbep_qpi_hw_config (struct intel_uncore_box * box , struct perf_event * event )
@@ -2750,22 +2749,33 @@ static struct intel_uncore_type *hswep_msr_uncores[] = {
27502749 NULL ,
27512750};
27522751
2753- void hswep_uncore_cpu_init (void )
2752+ #define HSWEP_PCU_DID 0x2fc0
2753+ #define HSWEP_PCU_CAPID4_OFFET 0x94
2754+ #define hswep_get_chop (_cap ) (((_cap) >> 6) & 0x3)
2755+
2756+ static bool hswep_has_limit_sbox (unsigned int device )
27542757{
2755- int pkg = boot_cpu_data .logical_proc_id ;
2758+ struct pci_dev * dev = pci_get_device (PCI_VENDOR_ID_INTEL , device , NULL );
2759+ u32 capid4 ;
2760+
2761+ if (!dev )
2762+ return false;
2763+
2764+ pci_read_config_dword (dev , HSWEP_PCU_CAPID4_OFFET , & capid4 );
2765+ if (!hswep_get_chop (capid4 ))
2766+ return true;
27562767
2768+ return false;
2769+ }
2770+
2771+ void hswep_uncore_cpu_init (void )
2772+ {
27572773 if (hswep_uncore_cbox .num_boxes > boot_cpu_data .x86_max_cores )
27582774 hswep_uncore_cbox .num_boxes = boot_cpu_data .x86_max_cores ;
27592775
27602776 /* Detect 6-8 core systems with only two SBOXes */
2761- if (uncore_extra_pci_dev [pkg ].dev [HSWEP_PCI_PCU_3 ]) {
2762- u32 capid4 ;
2763-
2764- pci_read_config_dword (uncore_extra_pci_dev [pkg ].dev [HSWEP_PCI_PCU_3 ],
2765- 0x94 , & capid4 );
2766- if (((capid4 >> 6 ) & 0x3 ) == 0 )
2767- hswep_uncore_sbox .num_boxes = 2 ;
2768- }
2777+ if (hswep_has_limit_sbox (HSWEP_PCU_DID ))
2778+ hswep_uncore_sbox .num_boxes = 2 ;
27692779
27702780 uncore_msr_uncores = hswep_msr_uncores ;
27712781}
@@ -3028,11 +3038,6 @@ static const struct pci_device_id hswep_uncore_pci_ids[] = {
30283038 .driver_data = UNCORE_PCI_DEV_DATA (UNCORE_EXTRA_PCI_DEV ,
30293039 SNBEP_PCI_QPI_PORT1_FILTER ),
30303040 },
3031- { /* PCU.3 (for Capability registers) */
3032- PCI_DEVICE (PCI_VENDOR_ID_INTEL , 0x2fc0 ),
3033- .driver_data = UNCORE_PCI_DEV_DATA (UNCORE_EXTRA_PCI_DEV ,
3034- HSWEP_PCI_PCU_3 ),
3035- },
30363041 { /* end: all zeroes */ }
30373042};
30383043
@@ -3124,27 +3129,18 @@ static struct event_constraint bdx_uncore_pcu_constraints[] = {
31243129 EVENT_CONSTRAINT_END
31253130};
31263131
3132+ #define BDX_PCU_DID 0x6fc0
3133+
31273134void bdx_uncore_cpu_init (void )
31283135{
3129- int pkg = topology_phys_to_logical_pkg (boot_cpu_data .phys_proc_id );
3130-
31313136 if (bdx_uncore_cbox .num_boxes > boot_cpu_data .x86_max_cores )
31323137 bdx_uncore_cbox .num_boxes = boot_cpu_data .x86_max_cores ;
31333138 uncore_msr_uncores = bdx_msr_uncores ;
31343139
3135- /* BDX-DE doesn't have SBOX */
3136- if (boot_cpu_data .x86_model == 86 ) {
3137- uncore_msr_uncores [BDX_MSR_UNCORE_SBOX ] = NULL ;
31383140 /* Detect systems with no SBOXes */
3139- } else if (uncore_extra_pci_dev [pkg ].dev [HSWEP_PCI_PCU_3 ]) {
3140- struct pci_dev * pdev ;
3141- u32 capid4 ;
3142-
3143- pdev = uncore_extra_pci_dev [pkg ].dev [HSWEP_PCI_PCU_3 ];
3144- pci_read_config_dword (pdev , 0x94 , & capid4 );
3145- if (((capid4 >> 6 ) & 0x3 ) == 0 )
3146- bdx_msr_uncores [BDX_MSR_UNCORE_SBOX ] = NULL ;
3147- }
3141+ if ((boot_cpu_data .x86_model == 86 ) || hswep_has_limit_sbox (BDX_PCU_DID ))
3142+ uncore_msr_uncores [BDX_MSR_UNCORE_SBOX ] = NULL ;
3143+
31483144 hswep_uncore_pcu .constraints = bdx_uncore_pcu_constraints ;
31493145}
31503146
@@ -3365,11 +3361,6 @@ static const struct pci_device_id bdx_uncore_pci_ids[] = {
33653361 .driver_data = UNCORE_PCI_DEV_DATA (UNCORE_EXTRA_PCI_DEV ,
33663362 BDX_PCI_QPI_PORT2_FILTER ),
33673363 },
3368- { /* PCU.3 (for Capability registers) */
3369- PCI_DEVICE (PCI_VENDOR_ID_INTEL , 0x6fc0 ),
3370- .driver_data = UNCORE_PCI_DEV_DATA (UNCORE_EXTRA_PCI_DEV ,
3371- HSWEP_PCI_PCU_3 ),
3372- },
33733364 { /* end: all zeroes */ }
33743365};
33753366
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