@@ -10,8 +10,20 @@ const PIC1_DATA: Port<u8> = Port::new(0x21);
1010const PIC2_COMMAND : Port < u8 > = Port :: new ( 0xa0 ) ;
1111const PIC2_DATA : Port < u8 > = Port :: new ( 0xa1 ) ;
1212
13- pub const PIC1_INTERRUPT_OFFSET : u8 = 32 ;
14- const PIC2_INTERRUPT_OFFSET : u8 = 40 ;
13+ /// PIC1 interrupt offset.
14+ ///
15+ /// Vectors 0 through 31 in the IDT are defined or reserved by the
16+ /// architecture. Thus, user-defined interrupts are vectors 32 through 255. We
17+ /// choose to map the 16 interrupts by the two PICs at the beginning of the
18+ /// user-defined interrupts.
19+ pub const PIC1_OFFSET : u8 = 32 ;
20+
21+ /// PIC2 interrupt offset.
22+ ///
23+ /// Each PIC handles 8 interrupts.
24+ /// We set up the two PICs to be contiguous.
25+ const PIC2_OFFSET : u8 = 40 ;
26+
1527const SPURIOUS_IRQ_NUMBER : u8 = 7 ;
1628
1729/// End-Of-Interrupt Command for an Intel 8259 Programmable Interrupt Controller (PIC).
@@ -42,10 +54,10 @@ pub fn init() {
4254 // This is especially true for real hardware. So provide a handler for them.
4355 unsafe {
4456 let mut idt = IDT . lock ( ) ;
45- idt[ PIC1_INTERRUPT_OFFSET + SPURIOUS_IRQ_NUMBER ]
57+ idt[ PIC1_OFFSET + SPURIOUS_IRQ_NUMBER ]
4658 . set_handler_fn ( spurious_interrupt_on_master)
4759 . set_stack_index ( 0 ) ;
48- idt[ PIC2_INTERRUPT_OFFSET + SPURIOUS_IRQ_NUMBER ]
60+ idt[ PIC2_OFFSET + SPURIOUS_IRQ_NUMBER ]
4961 . set_handler_fn ( spurious_interrupt_on_slave)
5062 . set_stack_index ( 0 ) ;
5163
@@ -65,8 +77,8 @@ pub fn init() {
6577 pic2_command. write ( 0x11 ) ;
6678
6779 // Map PIC1 to interrupt numbers >= 32 and PIC2 to interrupt numbers >= 40.
68- pic1_data. write ( PIC1_INTERRUPT_OFFSET ) ;
69- pic2_data. write ( PIC2_INTERRUPT_OFFSET ) ;
80+ pic1_data. write ( PIC1_OFFSET ) ;
81+ pic2_data. write ( PIC2_OFFSET ) ;
7082
7183 // Configure PIC1 as master and PIC2 as slave.
7284 pic1_data. write ( 0x04 ) ;
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