feat(x86_64): add PVH support

Author: mkroening

.vscode/settings.json

@@ -16,13 +16,13 @@
         "--message-format=json",
         "--all-targets",
         "-Zbuild-std=core,alloc",
-        "--target=aarch64-unknown-none-softfloat",
-        "--target=riscv64gc-unknown-none-elf",
+        // "--target=aarch64-unknown-none-softfloat",
+        // "--target=riscv64gc-unknown-none-elf",
         "--target=x86_64-unknown-none",
     ],
     "rust-analyzer.check.targets": [
-        "aarch64-unknown-none-softfloat",
-        "riscv64gc-unknown-none-elf",
+        // "aarch64-unknown-none-softfloat",
+        // "riscv64gc-unknown-none-elf",
         "x86_64-unknown-none",
     ],
 }

Cargo.lock

@@ -338,6 +338,7 @@ features = [
 
 [target.'cfg(target_arch = "x86_64")'.dependencies]
 free-list = { version = "0.3", features = ["x86_64"] }
+pvh = "0.1"
 raw-cpuid = "11"
 uart_16550 = { version = "0.6", features = ["embedded-io"] }
 x86_64 = "0.15"

Cargo.toml

@@ -12,6 +12,7 @@ use x86_64::registers::control::{Cr0, Cr4};
 use crate::arch::x86_64::kernel::core_local::*;
 use crate::env::{self, is_uhyve};
 
+pub mod pvh;
 #[cfg(feature = "acpi")]
 pub mod acpi;
 pub mod apic;
@@ -192,7 +193,8 @@ unsafe extern "C" fn pre_init(boot_info: Option<&'static RawBootInfo>, cpu_id: u
 	}
 
 	if cpu_id == 0 {
-		env::set_boot_info(*boot_info.unwrap());
+		// env::set_boot_info(*boot_info.unwrap());
+		println!("Foo");
 
 		crate::boot_processor_main()
 	} else {

src/arch/x86_64/kernel/mod.rs

@@ -0,0 +1,51 @@
+use x86_64::structures::gdt::{Descriptor, GlobalDescriptorTable, SegmentSelector};
+
+const GDT_LEN: usize = 3;
+
+pub(super) static GDT: GlobalDescriptorTable<GDT_LEN> = Gdt::gdt();
+
+pub(super) static GDT_PTR: DescriptorTablePointer<'static, GDT_LEN> =
+    DescriptorTablePointer::new(&GDT);
+
+pub(super) struct Gdt;
+
+impl Gdt {
+    const fn create() -> (
+        GlobalDescriptorTable<GDT_LEN>,
+        SegmentSelector,
+        SegmentSelector,
+    ) {
+        let mut gdt = GlobalDescriptorTable::empty();
+        let kernel_code_selector = gdt.append(Descriptor::kernel_code_segment());
+        let kernel_data_selector = gdt.append(Descriptor::kernel_data_segment());
+        (gdt, kernel_code_selector, kernel_data_selector)
+    }
+
+    pub(super) const fn gdt() -> GlobalDescriptorTable<GDT_LEN> {
+        Self::create().0
+    }
+
+    pub(super) const fn kernel_code_selector() -> SegmentSelector {
+        Self::create().1
+    }
+
+    pub(super) const fn kernel_data_selector() -> SegmentSelector {
+        Self::create().2
+    }
+}
+
+#[derive(Debug, Clone, Copy)]
+#[repr(C, packed(2))]
+pub(super) struct DescriptorTablePointer<'a, const MAX: usize> {
+    limit: u16,
+    base: &'a GlobalDescriptorTable<MAX>,
+}
+
+impl<'a, const MAX: usize> DescriptorTablePointer<'a, MAX> {
+    const fn new(gdt: &'a GlobalDescriptorTable<MAX>) -> Self {
+        Self {
+            limit: gdt.limit(),
+            base: gdt,
+        }
+    }
+}

src/arch/x86_64/kernel/pvh/gdt.rs

@@ -0,0 +1,76 @@
+mod gdt;
+mod page_tables;
+mod stack;
+
+use core::sync::atomic::{AtomicU32, Ordering};
+
+use hermit_entry::boot_info::{BootInfo, HardwareInfo, LoadInfo, PlatformInfo, SerialPortBase};
+use pvh::start_info::reader::{IdentityMap, StartInfoReader};
+
+use self::stack::{STACK, Stack};
+use crate::env::setboot_info2;
+use crate::kernel::pre_init;
+
+/// The PVH entry point.
+#[unsafe(naked)]
+pub(crate) unsafe extern "C" fn pvh_start32() -> ! {
+	core::arch::naked_asm!(
+		".code32",
+		include_str!("pvh_start32.s"),
+		".code64",
+
+		level_4_table = sym page_tables::LEVEL_4_TABLE,
+		gdt_ptr = sym gdt::GDT_PTR,
+		kernel_data_selector = const gdt::Gdt::kernel_data_selector().0,
+
+		stack = sym STACK,
+		stack_size = const size_of::<Stack>(),
+		kernel_code_selector = const gdt::Gdt::kernel_code_selector().0,
+		rust_start = sym rust_start,
+	);
+}
+
+pvh::xen_elfnote_phys32_entry!(pvh_start32);
+
+/// The native ELF entry point.
+#[unsafe(no_mangle)]
+#[unsafe(naked)]
+unsafe extern "C" fn _start() -> ! {
+	core::arch::naked_asm!("2: jmp 2b");
+}
+
+static START_INFO_PADDR: AtomicU32 = AtomicU32::new(0);
+
+pub fn start_info<'a>() -> StartInfoReader<'a, IdentityMap> {
+	let paddr = START_INFO_PADDR.load(Ordering::Relaxed);
+	unsafe { StartInfoReader::from_paddr_identity(paddr).unwrap() }
+}
+
+/// The Rust entry point.
+unsafe extern "C" fn rust_start(start_info_paddr: u32) -> ! {
+	START_INFO_PADDR.store(start_info_paddr, Ordering::Relaxed);
+
+	let start_info = start_info();
+
+	println!("Start info:\n{start_info:#?}");
+
+	let boot_info = BootInfo {
+		hardware_info: HardwareInfo {
+			phys_addr_range: 0..0,
+			serial_port_base: SerialPortBase::new(0x3f8),
+			device_tree: None,
+		},
+		// This is not used by the kernel anymore.
+		load_info: LoadInfo {
+			kernel_image_addr_range: 0..0,
+			tls_info: None,
+		},
+		platform_info: PlatformInfo::Fdt,
+	};
+
+	println!("boot_info = {boot_info:#x?}");
+
+	setboot_info2(boot_info);
+
+	unsafe { pre_init(None, 0) }
+}

src/arch/x86_64/kernel/pvh/mod.rs

@@ -0,0 +1,65 @@
+//! Page Tables.
+//!
+//! This module defines the page tables that we switch to by setting `CR3` to
+//! `LEVEL_4_TABLE`. Specifically, we map the first GiB of virtual memory using
+//! 512 2-MiB pages. 2-MiB pages are supported on every x86-64 CPU.
+//!
+//! # Current implementation
+//!
+//! Some page tables need to point to other page tables, but also contain flags.
+//! We do this by adding the flags as bytes to the pointer, which is possible in
+//! const-eval. The resulting expression is relocatable.
+//!
+//! Casting pointers to integers is not possible in const-eval. Asserting that
+//! all flag bits in the address are 0 is not possible. Using a bitwise OR (`|`)
+//! operation cannot be expressed and would not be relocatable.
+//!
+//! For details, see this discussion: [rust-lang/rust#51910 (comment)].
+//!
+//! [rust-lang/rust#51910 (comment)]: https://github.com/rust-lang/rust/issues/51910#issuecomment-1013271838
+
+use core::ptr;
+
+use x86_64::structures::paging::{PageSize, PageTableFlags, Size2MiB};
+
+const TABLE_FLAGS: PageTableFlags = PageTableFlags::PRESENT.union(PageTableFlags::WRITABLE);
+const PAGE_FLAGS: PageTableFlags = TABLE_FLAGS.union(PageTableFlags::HUGE_PAGE);
+
+pub(super) static mut LEVEL_4_TABLE: PageTable = {
+    let flags = TABLE_FLAGS.bits() as usize;
+
+    let mut page_table = [ptr::null_mut(); _];
+
+    page_table[0] = (&raw mut LEVEL_3_TABLE).wrapping_byte_add(flags).cast();
+
+    PageTable(page_table)
+};
+
+static mut LEVEL_3_TABLE: PageTable = {
+    let flags = TABLE_FLAGS.bits() as usize;
+
+    let mut page_table = [ptr::null_mut(); _];
+
+    page_table[0] = (&raw mut LEVEL_2_TABLE).wrapping_byte_add(flags).cast();
+
+    PageTable(page_table)
+};
+
+static mut LEVEL_2_TABLE: PageTable = {
+    let flags: usize = PAGE_FLAGS.bits() as usize;
+
+    let mut page_table = [ptr::null_mut(); _];
+
+    let mut i = 0;
+    while i < page_table.len() {
+        let addr = i * Size2MiB::SIZE as usize;
+        page_table[i] = ptr::with_exposed_provenance_mut(addr + flags);
+        i += 1;
+    }
+
+    PageTable(page_table)
+};
+
+#[repr(align(0x1000))]
+#[repr(C)]
+pub(super) struct PageTable([*mut (); 512]);

src/arch/x86_64/kernel/pvh/page_tables.rs

@@ -0,0 +1,64 @@
+    // Load level 4 page table into cr3
+    mov eax, offset {level_4_table}
+    mov cr3, eax
+    cli
+
+    // Enable physical address extensions
+.set CR4_FLAGS_PHYSICAL_ADDRESS_EXTENSION, 1 << 5
+    mov eax, cr4
+    or eax, CR4_FLAGS_PHYSICAL_ADDRESS_EXTENSION
+    mov cr4, eax
+
+    // Switch to compatibility mode
+.set EFER_MSR, 0xc0000080
+.set EFER_FLAGS_LONG_MODE_ENABLE, 1 << 8
+    mov ecx, EFER_MSR
+    rdmsr
+    or eax, EFER_FLAGS_LONG_MODE_ENABLE
+    wrmsr
+
+    // Enable paging and protected mode
+.set CR0_FLAGS_PROTECTED_MODE_ENABLE, 1
+.set CR0_FLAGS_PAGING, 1 << 31
+    mov eax, cr0
+    or eax, CR0_FLAGS_PROTECTED_MODE_ENABLE | CR0_FLAGS_PAGING
+    mov cr0, eax
+
+
+    # Set CR0 (PM-bit is already set)
+    mov eax, cr0
+    and eax, ~(1 << 2)      # disable FPU emulation
+    or eax, (1 << 1)        # enable FPU montitoring
+    and eax, ~(1 << 30)     # enable caching
+    and eax, ~(1 << 29)     # disable write through caching
+    and eax, ~(1 << 16)	    # allow kernel write access to read-only pages
+    or eax, (1 << 31)       # enable paging
+    mov cr0, eax
+
+    // Load the GDT
+    lgdt [offset {gdt_ptr}]
+
+    // Load the segment registers
+    mov ax, {kernel_data_selector}
+    mov ds, eax
+    mov es, eax
+    mov fs, eax
+    mov gs, eax
+    mov ss, eax
+
+    // ebx contains the start info physical address
+    // Jump to rust_start with paddr as first argument
+    mov edi, ebx
+
+    // Set up the stack
+    mov esp, offset {stack}
+    add esp, {stack_size}
+
+    // We need to do a far jump, but LLVM does not support absolute far jumps
+    // in Intel syntax yet: https://github.com/llvm/llvm-project/issues/46048
+    // We could switch to AT&T syntax for the unsupported line of code but
+    // using far returns is more flexible anyway.
+    push {kernel_code_selector}
+    mov eax, offset {rust_start}
+    push eax
+    retf

src/arch/x86_64/kernel/pvh/pvh_start32.s

@@ -0,0 +1,6 @@
+use core::mem::MaybeUninit;
+
+pub(super) static mut STACK: MaybeUninit<Stack> = MaybeUninit::uninit();
+
+#[repr(C, align(0x1000))]
+pub(super) struct Stack([u8; 0x8000]);

src/arch/x86_64/kernel/pvh/stack.rs

@@ -14,7 +14,7 @@ use crate::errno::Errno;
 #[cfg(feature = "pci")]
 const SERIAL_IRQ: u8 = 4;
 
-static UART_DEVICE: Lazy<InterruptTicketMutex<UartDevice>> =
+pub static UART_DEVICE: Lazy<InterruptTicketMutex<UartDevice>> =
 	Lazy::new(|| unsafe { InterruptTicketMutex::new(UartDevice::new()) });
 
 struct UartDevice {
@@ -24,11 +24,12 @@ struct UartDevice {
 
 impl UartDevice {
 	pub unsafe fn new() -> Self {
-		let base = crate::env::boot_info()
-			.hardware_info
-			.serial_port_base
-			.unwrap()
-			.get();
+		// let base = crate::env::boot_info()
+		// 	.hardware_info
+		// 	.serial_port_base
+		// 	.unwrap()
+		// 	.get();
+		let base = 0x3f8;
 		let mut uart = unsafe { Uart16550::new_port(base).unwrap() };
 		uart.init(Config::default()).ok();
 		// Once we have a fallback destination for output,