feat(x86_64): add PVH support

Author: mkroening

.vscode/settings.json

@@ -16,13 +16,13 @@
         "--message-format=json",
         "--all-targets",
         "-Zbuild-std=core,alloc",
-        "--target=aarch64-unknown-none-softfloat",
-        "--target=riscv64gc-unknown-none-elf",
+        // "--target=aarch64-unknown-none-softfloat",
+        // "--target=riscv64gc-unknown-none-elf",
         "--target=x86_64-unknown-none",
     ],
     "rust-analyzer.check.targets": [
-        "aarch64-unknown-none-softfloat",
-        "riscv64gc-unknown-none-elf",
+        // "aarch64-unknown-none-softfloat",
+        // "riscv64gc-unknown-none-elf",
         "x86_64-unknown-none",
     ],
 }

Cargo.lock

@@ -310,6 +310,7 @@ mem-barrier = { version = "0.1.0", optional = true, features = ["nightly"] }
 num_enum = { version = "0.7", default-features = false }
 pci-ids = { version = "0.2", optional = true }
 pci_types = { version = "0.10" }
+pvh = { path = "../../pvh" }
 rand_chacha = { version = "0.10", default-features = false }
 shell-words = { version = "1.1", default-features = false }
 simple-shell = { version = "0.0.1", optional = true }

Cargo.toml

@@ -12,6 +12,7 @@ use x86_64::registers::control::{Cr0, Cr4};
 use crate::arch::x86_64::kernel::core_local::*;
 use crate::env::{self, is_uhyve};
 
+pub mod pvh;
 #[cfg(feature = "acpi")]
 pub mod acpi;
 pub mod apic;
@@ -201,7 +202,8 @@ unsafe extern "C" fn pre_init(boot_info: Option<&'static RawBootInfo>, cpu_id: u
 	}
 
 	if cpu_id == 0 {
-		env::set_boot_info(*boot_info.unwrap());
+		// env::set_boot_info(*boot_info.unwrap());
+		println!("Foo");
 
 		crate::boot_processor_main()
 	} else {

src/arch/x86_64/kernel/mod.rs

@@ -0,0 +1,51 @@
+use x86_64::structures::gdt::{Descriptor, GlobalDescriptorTable, SegmentSelector};
+
+const GDT_LEN: usize = 3;
+
+pub(super) static GDT: GlobalDescriptorTable<GDT_LEN> = Gdt::gdt();
+
+pub(super) static GDT_PTR: DescriptorTablePointer<'static, GDT_LEN> =
+    DescriptorTablePointer::new(&GDT);
+
+pub(super) struct Gdt;
+
+impl Gdt {
+    const fn create() -> (
+        GlobalDescriptorTable<GDT_LEN>,
+        SegmentSelector,
+        SegmentSelector,
+    ) {
+        let mut gdt = GlobalDescriptorTable::empty();
+        let kernel_code_selector = gdt.append(Descriptor::kernel_code_segment());
+        let kernel_data_selector = gdt.append(Descriptor::kernel_data_segment());
+        (gdt, kernel_code_selector, kernel_data_selector)
+    }
+
+    pub(super) const fn gdt() -> GlobalDescriptorTable<GDT_LEN> {
+        Self::create().0
+    }
+
+    pub(super) const fn kernel_code_selector() -> SegmentSelector {
+        Self::create().1
+    }
+
+    pub(super) const fn kernel_data_selector() -> SegmentSelector {
+        Self::create().2
+    }
+}
+
+#[derive(Debug, Clone, Copy)]
+#[repr(C, packed(2))]
+pub(super) struct DescriptorTablePointer<'a, const MAX: usize> {
+    limit: u16,
+    base: &'a GlobalDescriptorTable<MAX>,
+}
+
+impl<'a, const MAX: usize> DescriptorTablePointer<'a, MAX> {
+    const fn new(gdt: &'a GlobalDescriptorTable<MAX>) -> Self {
+        Self {
+            limit: gdt.limit(),
+            base: gdt,
+        }
+    }
+}

src/arch/x86_64/kernel/pvh/gdt.rs

@@ -0,0 +1,185 @@
+mod gdt;
+mod page_tables;
+mod stack;
+
+use core::ptr::NonNull;
+use core::sync::atomic::{AtomicU32, Ordering};
+
+use hermit_entry::boot_info::{BootInfo, HardwareInfo, LoadInfo, PlatformInfo, SerialPortBase, TlsInfo};
+use pvh::start_info::reader::{IdentityMap, StartInfoReader};
+
+use self::stack::{STACK, Stack};
+use crate::env::setboot_info2;
+use crate::kernel::pre_init;
+
+/// The PVH entry point.
+#[unsafe(naked)]
+pub(crate) unsafe extern "C" fn pvh_start32() -> ! {
+	core::arch::naked_asm!(
+		".code32",
+		include_str!("pvh_start32.s"),
+		".code64",
+
+		level_4_table = sym page_tables::LEVEL_4_TABLE,
+		gdt_ptr = sym gdt::GDT_PTR,
+		kernel_data_selector = const gdt::Gdt::kernel_data_selector().0,
+
+		stack = sym STACK,
+		stack_size = const size_of::<Stack>(),
+		kernel_code_selector = const gdt::Gdt::kernel_code_selector().0,
+		rust_start = sym rust_start,
+	);
+}
+
+pvh::xen_elfnote_phys32_entry!(pvh_start32);
+
+/// The native ELF entry point.
+#[unsafe(no_mangle)]
+#[unsafe(naked)]
+unsafe extern "C" fn _start() -> ! {
+	core::arch::naked_asm!("2: jmp 2b");
+}
+
+static START_INFO_PADDR: AtomicU32 = AtomicU32::new(0);
+
+pub fn start_info<'a>() -> StartInfoReader<'a, IdentityMap> {
+	let paddr = START_INFO_PADDR.load(Ordering::Relaxed);
+	unsafe { StartInfoReader::from_paddr_identity(paddr).unwrap() }
+}
+
+/// The Rust entry point.
+unsafe extern "C" fn rust_start(start_info_paddr: u32) -> ! {
+	START_INFO_PADDR.store(start_info_paddr, Ordering::Relaxed);
+
+	let start_info = start_info();
+
+	println!("Start info:\n{start_info:#?}");
+
+	dbg!(tdata());
+
+	let boot_info = BootInfo {
+		hardware_info: HardwareInfo {
+			phys_addr_range: 0..0,
+			serial_port_base: SerialPortBase::new(0x3f8),
+			device_tree: None,
+		},
+		load_info: LoadInfo {
+			kernel_image_addr_range: executable_start() as u64..executable_end() as u64,
+			tls_info: dbg!(find_tls_ranges()),
+		},
+		platform_info: PlatformInfo::Fdt,
+	};
+
+	println!("boot_info = {boot_info:#x?}");
+
+	setboot_info2(boot_info);
+
+	unsafe { pre_init(None, 0) }
+}
+
+pub fn executable_start() -> *mut () {
+	unsafe extern "C" {
+		static mut __executable_start: u8;
+	}
+
+	(&raw mut __executable_start).cast::<()>()
+}
+
+pub fn executable_end() -> *mut () {
+	unsafe extern "C" {
+		static mut _end: u8;
+	}
+
+	(&raw mut _end).cast::<()>()
+}
+
+pub fn tdata() -> *mut () {
+	unsafe extern "C" {
+		static mut __ehdr_start: u8;
+	}
+
+	(&raw mut __ehdr_start).cast::<()>()
+}
+
+
+use core::slice;
+
+const PT_LOAD: u32 = 1;
+const PT_TLS:  u32 = 7;
+
+#[repr(C)]
+struct Elf64Ehdr {
+    e_ident: [u8; 16],
+    e_type: u16,
+    e_machine: u16,
+    e_version: u32,
+    e_entry: u64,
+    e_phoff: u64,
+    e_shoff: u64,
+    e_flags: u32,
+    e_ehsize: u16,
+    e_phentsize: u16,
+    e_phnum: u16,
+    e_shentsize: u16,
+    e_shnum: u16,
+    e_shstrndx: u16,
+}
+
+#[repr(C)]
+struct Elf64Phdr {
+    p_type: u32,
+    p_flags: u32,
+    p_offset: u64,
+    p_vaddr: u64,
+    p_paddr: u64,
+    p_filesz: u64,
+    p_memsz: u64,
+    p_align: u64,
+}
+
+// Provided by the default ELF linker scripts for executables
+unsafe extern "C" {
+    static __ehdr_start: Elf64Ehdr;
+}
+
+#[derive(Debug, Clone, Copy)]
+pub struct TlsRanges {
+    pub tdata_start: *const u8,
+    pub tdata_end:   *const u8,
+    pub tbss_start:  *const u8,
+    pub tbss_end:    *const u8,
+}
+
+unsafe fn find_tls_ranges() -> Option<TlsInfo> {
+    let ehdr = &__ehdr_start as *const Elf64Ehdr;
+    let ehdr_ref = &*ehdr;
+
+    // Optional: check ELF magic
+    if ehdr_ref.e_ident[0..4] != [0x7f, b'E', b'L', b'F'] {
+        return None;
+    }
+
+    // Program headers
+    let phdr_ptr = (ehdr as *const u8).add(ehdr_ref.e_phoff as usize) as *const Elf64Phdr;
+    let phdrs = slice::from_raw_parts(phdr_ptr, ehdr_ref.e_phnum as usize);
+
+    // Find PT_LOAD segment that contains file offset 0 (usually p_offset == 0)
+    let first_load = phdrs
+        .iter()
+        .find(|ph| ph.p_type == PT_LOAD && ph.p_offset == 0)?
+        ;
+
+    // Compute load base of the main executable
+    let ehdr_addr = &__ehdr_start as *const _ as usize;
+    let base = ehdr_addr.wrapping_sub(first_load.p_vaddr as usize);
+
+    // Find PT_TLS segment
+    let tls_ph = phdrs.iter().find(|ph| ph.p_type == PT_TLS)?;
+
+    let tdata_start = (base + tls_ph.p_vaddr as usize) as *const u8;
+    let tdata_end   = tdata_start.add(tls_ph.p_filesz as usize);
+    let tbss_start  = tdata_end;
+    let tbss_end    = tdata_start.add(tls_ph.p_memsz as usize);
+
+    Some(TlsInfo { start: tls_ph.p_vaddr, filesz: tls_ph.p_filesz, memsz: tls_ph.p_memsz, align: tls_ph.p_align })
+}

src/arch/x86_64/kernel/pvh/mod.rs

@@ -0,0 +1,65 @@
+//! Page Tables.
+//!
+//! This module defines the page tables that we switch to by setting `CR3` to
+//! `LEVEL_4_TABLE`. Specifically, we map the first GiB of virtual memory using
+//! 512 2-MiB pages. 2-MiB pages are supported on every x86-64 CPU.
+//!
+//! # Current implementation
+//!
+//! Some page tables need to point to other page tables, but also contain flags.
+//! We do this by adding the flags as bytes to the pointer, which is possible in
+//! const-eval. The resulting expression is relocatable.
+//!
+//! Casting pointers to integers is not possible in const-eval. Asserting that
+//! all flag bits in the address are 0 is not possible. Using a bitwise OR (`|`)
+//! operation cannot be expressed and would not be relocatable.
+//!
+//! For details, see this discussion: [rust-lang/rust#51910 (comment)].
+//!
+//! [rust-lang/rust#51910 (comment)]: https://github.com/rust-lang/rust/issues/51910#issuecomment-1013271838
+
+use core::ptr;
+
+use x86_64::structures::paging::{PageSize, PageTableFlags, Size2MiB};
+
+const TABLE_FLAGS: PageTableFlags = PageTableFlags::PRESENT.union(PageTableFlags::WRITABLE);
+const PAGE_FLAGS: PageTableFlags = TABLE_FLAGS.union(PageTableFlags::HUGE_PAGE);
+
+pub(super) static mut LEVEL_4_TABLE: PageTable = {
+    let flags = TABLE_FLAGS.bits() as usize;
+
+    let mut page_table = [ptr::null_mut(); _];
+
+    page_table[0] = (&raw mut LEVEL_3_TABLE).wrapping_byte_add(flags).cast();
+
+    PageTable(page_table)
+};
+
+static mut LEVEL_3_TABLE: PageTable = {
+    let flags = TABLE_FLAGS.bits() as usize;
+
+    let mut page_table = [ptr::null_mut(); _];
+
+    page_table[0] = (&raw mut LEVEL_2_TABLE).wrapping_byte_add(flags).cast();
+
+    PageTable(page_table)
+};
+
+static mut LEVEL_2_TABLE: PageTable = {
+    let flags: usize = PAGE_FLAGS.bits() as usize;
+
+    let mut page_table = [ptr::null_mut(); _];
+
+    let mut i = 0;
+    while i < page_table.len() {
+        let addr = i * Size2MiB::SIZE as usize;
+        page_table[i] = ptr::with_exposed_provenance_mut(addr + flags);
+        i += 1;
+    }
+
+    PageTable(page_table)
+};
+
+#[repr(align(0x1000))]
+#[repr(C)]
+pub(super) struct PageTable([*mut (); 512]);