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1. PADLOCK_PROJECT_GIAN_FPGA_INTERFACING PADLOCK_PROJECT_GIAN_FPGA_INTERFACING Public template

   This project deals with interfacing of Keypad with RISC-V cpu programmed in a FPGA

   TL-Verilog

2. risc_v_cpu_user_demo_gian risc_v_cpu_user_demo_gian Public

   This project involves designing a RISC-V CPU using the Makerchip platform, implementing a minimalistic architecture suitable for ASIC and FPGA applications. It demonstrates core principles of RISC-…

   TL-Verilog