Flush tlb from host

Signed-off-by: Ludvig Liljenberg <4257730+ludfjig@users.noreply.github.com>

Author: ludfjig

src/hyperlight_host/src/hypervisor/virtual_machine/whp.rs

@@ -729,6 +729,22 @@ impl VirtualMachine for WhpVm {
             WHvResetPartition(self.partition)
                 .map_err(|e| RegisterError::ResetPartition(e.into()))?;
 
+            // WHvResetPartition resets the VMCB but may not update the
+            // hypervisor's internal register-change tracking used for
+            // TLB flush decisions on AMD SVM. Explicitly re-announce
+            // the post-reset CR0 (PG=0) via the WHP API so that the
+            // subsequent restore_sregs() write of CR0 with PG=1 is
+            // detected as a paging-mode change, triggering
+            // SVM_TLB_FLUSH_CURRENT_ASID on the next VMRUN.
+            let post_reset_sregs = self.sregs()?;
+            self.set_registers(&[(
+                WHvX64RegisterCr0,
+                Align16(WHV_REGISTER_VALUE {
+                    Reg64: post_reset_sregs.cr0,
+                }),
+            )])
+            .map_err(|e| RegisterError::ResetPartition(e.into()))?;
+
             // WHvResetPartition resets LAPIC to power-on defaults.
             // Re-initialize it when LAPIC emulation is active.
             #[cfg(feature = "hw-interrupts")]