|
| 1 | +<!-- |
| 2 | +SPDX-License-Identifier: CC-BY-SA-4.0 |
| 3 | +SPDX-FileCopyrightText: 2025-2026 Jonathan D.A. Jewell <j.d.a.jewell@open.ac.uk> |
| 4 | +--> |
| 5 | + |
| 6 | +# What Is This? |
| 7 | + |
| 8 | +Halideiser compiles image and video processing pipelines to optimised |
| 9 | +[Halide](https://halide-lang.org) schedules. You describe your pipeline |
| 10 | +stages in `halideiser.toml` — blur, sharpen, resize, edge detect, colour |
| 11 | +transform, convolution — and Halideiser generates the Halide algorithm |
| 12 | +definitions, auto-tunes the schedule for your target hardware, and |
| 13 | +produces optimised native code. |
| 14 | + |
| 15 | +Halide (by Jonathan Ragan-Kelley et al., MIT/Google) separates the |
| 16 | +*algorithm* (what to compute) from the *schedule* (how to compute it on |
| 17 | +hardware). This separation enables 10–100x speedups over hand-tuned C by |
| 18 | +letting the compiler explore tiling, vectorisation, parallelism, and |
| 19 | +memory layout choices automatically. Halideiser makes this power |
| 20 | +accessible without Halide expertise. |
| 21 | + |
| 22 | +# How It Works |
| 23 | + |
| 24 | +```text |
| 25 | +halideiser.toml (pipeline description) |
| 26 | + │ |
| 27 | + ▼ |
| 28 | + Pipeline Parser (validate stages, data flow, dimensions) |
| 29 | + │ |
| 30 | + ▼ |
| 31 | + Idris2 ABI Proofs (prove pipeline correctness, buffer safety) |
| 32 | + │ |
| 33 | + ▼ |
| 34 | + Halide Algorithm (Func definitions, Var bindings, Expr trees) |
| 35 | + Codegen (from pipeline stages) |
| 36 | + │ |
| 37 | + ▼ |
| 38 | + Schedule Generation (tile, vectorize, parallelize, compute_at, |
| 39 | + + Auto-Tuning store_at, reorder — search over schedule space) |
| 40 | + │ |
| 41 | + ▼ |
| 42 | + Compiled Pipeline (native code for target hardware) |
| 43 | +``` |
| 44 | + |
| 45 | +1. **Describe** your pipeline in `halideiser.toml` — stages, buffer |
| 46 | + dimensions, data types, target hardware |
| 47 | + |
| 48 | +2. **Validate** — the Idris2 ABI layer formally proves buffer bounds, |
| 49 | + dimension compatibility, and stage connectivity |
| 50 | + |
| 51 | +3. **Generate** — Halide algorithm code is emitted with `Func`, `Var`, |
| 52 | + and scheduling primitives |
| 53 | + |
| 54 | +4. **Tune** — the auto-tuner searches the schedule space (tile sizes, |
| 55 | + loop orders, parallelism) for optimal performance |
| 56 | + |
| 57 | +5. **Compile** — the tuned schedule is compiled to native code via LLVM |
| 58 | + |
| 59 | +# Halide Concepts |
| 60 | + |
| 61 | +Halideiser works with core Halide abstractions: |
| 62 | + |
| 63 | +- **Func** — a pure function defining what to compute at each pixel |
| 64 | + |
| 65 | +- **Var** — a dimension variable (x, y, channel, frame) |
| 66 | + |
| 67 | +- **Scheduling primitives** — control *how* to execute: |
| 68 | + |
| 69 | + - `tile(x,` `y,` `xi,` `yi,` `tx,` `ty)` — break loops into tiles for |
| 70 | + cache locality |
| 71 | + |
| 72 | + - `vectorize(xi,` `width)` — use SIMD instructions (SSE, AVX, NEON) |
| 73 | + |
| 74 | + - `parallelize(y)` — distribute rows across CPU cores |
| 75 | + |
| 76 | + - `compute_at(consumer,` `var)` — fuse producer into consumer loop |
| 77 | + |
| 78 | + - `store_at(consumer,` `var)` — control where intermediate buffers |
| 79 | + live |
| 80 | + |
| 81 | + - `reorder(vars…)` — change loop nesting order |
| 82 | + |
| 83 | + - `unroll(var,` `factor)` — unroll inner loops |
| 84 | + |
| 85 | + - `gpu_blocks` `/` `gpu_threads` — map to GPU compute grids |
| 86 | + |
| 87 | +# Hardware Targets |
| 88 | + |
| 89 | +| Target | Instructions / Backend | |
| 90 | +|--------------|--------------------------------------| |
| 91 | +| x86 SSE/AVX | 128–512-bit SIMD, auto-vectorisation | |
| 92 | +| ARM NEON/SVE | Mobile and embedded SIMD | |
| 93 | +| CUDA | NVIDIA GPU kernels | |
| 94 | +| OpenCL | Cross-vendor GPU compute | |
| 95 | +| WebAssembly | Browser-based image processing | |
| 96 | +| Metal | Apple GPU compute | |
| 97 | +| Vulkan | Cross-platform GPU compute | |
| 98 | + |
| 99 | +# Key Value |
| 100 | + |
| 101 | +- **10–100x faster** image and video processing without writing Halide |
| 102 | + by hand |
| 103 | + |
| 104 | +- **Automatic hardware scheduling** — SIMD, GPU, multi-core, all derived |
| 105 | + from one pipeline description |
| 106 | + |
| 107 | +- **No Halide expertise needed** — describe the pipeline, get the speed |
| 108 | + |
| 109 | +- **Formally verified** — Idris2 proofs guarantee buffer bounds and |
| 110 | + dimension safety before codegen |
| 111 | + |
| 112 | +- **Multi-target** — one pipeline compiles to x86, ARM, CUDA, OpenCL, |
| 113 | + WebAssembly |
| 114 | + |
| 115 | +# Use Cases |
| 116 | + |
| 117 | +- **Real-time video filters** — blur, sharpen, colour grade at 60fps+ |
| 118 | + |
| 119 | +- **Batch image processing** — resize, watermark, convert millions of |
| 120 | + images |
| 121 | + |
| 122 | +- **Medical imaging** — CT/MRI reconstruction, denoising, segmentation |
| 123 | + |
| 124 | +- **Computational photography** — HDR merge, demosaicing, lens |
| 125 | + correction |
| 126 | + |
| 127 | +- **Computer vision preprocessing** — edge detection, histogram |
| 128 | + equalisation, feature extraction |
| 129 | + |
| 130 | +# Architecture |
| 131 | + |
| 132 | +Follows the hyperpolymath -iser pattern (same as |
| 133 | +[Chapeliser](https://github.com/hyperpolymath/chapeliser)): |
| 134 | + |
| 135 | +- **Manifest** (`halideiser.toml`) — describe WHAT pipeline stages you |
| 136 | + need |
| 137 | + |
| 138 | +- **Pipeline Parser** (`src/manifest/`) — validate stage connectivity |
| 139 | + and buffer dimensions |
| 140 | + |
| 141 | +- **Idris2 ABI** (`src/interface/abi/`) — formal proofs of pipeline |
| 142 | + correctness, buffer layout, and scheduling safety |
| 143 | + |
| 144 | +- **Halide Codegen** (`src/codegen/`) — emit Halide `Func` / `Var` |
| 145 | + definitions and scheduling calls |
| 146 | + |
| 147 | +- **Zig FFI** (`src/interface/ffi/`) — C-ABI bridge for calling compiled |
| 148 | + pipelines from any language |
| 149 | + |
| 150 | +- **Rust CLI** (`src/main.rs`) — orchestrates parse, validate, generate, |
| 151 | + tune, and build |
| 152 | + |
| 153 | +User writes zero Halide code. Halideiser generates everything. |
| 154 | + |
| 155 | +Part of the [-iser family](https://github.com/hyperpolymath/iseriser) of |
| 156 | +acceleration frameworks. |
| 157 | + |
| 158 | +# Status |
| 159 | + |
| 160 | +**Pre-alpha.** Architecture defined, scaffolding in place, codegen |
| 161 | +pending. Codebase in progress — pipeline parser and Halide codegen are |
| 162 | +next. |
| 163 | + |
| 164 | +# Quick Start |
| 165 | + |
| 166 | +```bash |
| 167 | +# Initialise a manifest in the current directory |
| 168 | +halideiser init |
| 169 | + |
| 170 | +# Edit halideiser.toml to describe your pipeline stages |
| 171 | + |
| 172 | +# Validate the manifest |
| 173 | +halideiser validate |
| 174 | + |
| 175 | +# Generate Halide code and schedule |
| 176 | +halideiser generate |
| 177 | + |
| 178 | +# Build the compiled pipeline |
| 179 | +halideiser build --release |
| 180 | + |
| 181 | +# Run the pipeline |
| 182 | +halideiser run -- input.png output.png |
| 183 | +``` |
| 184 | + |
| 185 | +# License |
| 186 | + |
| 187 | +SPDX-License-Identifier: CC-BY-SA-4.0 |
0 commit comments