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| 1 | +// SPDX-License-Identifier: PMPL-2.0-or-later |
| 2 | += Unified Level System — TypeLL / VQL-UT / VeriSimDB / TypedQLiser / PanLL |
| 3 | +:toc: |
| 4 | + |
| 5 | +== Level Definitions |
| 6 | + |
| 7 | +[cols="1,3,3"] |
| 8 | +|=== |
| 9 | +| Level | Name | Criteria |
| 10 | + |
| 11 | +| L0 | Scaffold | Repo exists, no functional code |
| 12 | +| L1 | Spec | Specifications/types defined, no runtime |
| 13 | +| L2 | Partial | Some code works standalone, not connected |
| 14 | +| L3 | Core | Main engine works, tests pass, standalone |
| 15 | +| L4 | Integrated | Connected to adjacent systems, data flows |
| 16 | +| L5 | End-to-end | Full pipeline works across all systems |
| 17 | +| L6 | Tested | Point-to-point, end-to-end, aspect tests + benchmarks |
| 18 | +| L7 | Production | Published, documented, CI green, ready for users |
| 19 | +|=== |
| 20 | + |
| 21 | +== Current State (2026-03-21) |
| 22 | + |
| 23 | +[cols="2,1,3"] |
| 24 | +|=== |
| 25 | +| Component | Level | Notes |
| 26 | + |
| 27 | +| TypeLL core engine | L1 | Specs exist, no runtime type checker |
| 28 | +| TypedQLiser L5-10 | L1 | Levels 1-4 work, 5-10 need TypeLL |
| 29 | +| PanLL VQL panel | L0 | Does not exist |
| 30 | +| VQL-UT → VeriSimDB bridge | L2 | Parser works, no DB execution |
| 31 | +| VeriSimDB octad storage | L4 | Phase 4 validated, production tested |
| 32 | +| PanLL TypeLL panel | L2 | ReScript UI exists, not verified running |
| 33 | +| TypeLL-VQL bridge | L2 | Crate exists, depends on typell-core |
| 34 | +|=== |
| 35 | + |
| 36 | +== Level-Up Plan |
| 37 | + |
| 38 | +Round 1: Bring trailing (L0/L1) → L3:: |
| 39 | + 1. TypeLL core engine: implement type checker runtime |
| 40 | + 2. PanLL VQL panel: create the panel |
| 41 | + 3. TypedQLiser L5-10: implement with TypeLL backing |
| 42 | + |
| 43 | +Round 2: Bring all → L4 (integrated):: |
| 44 | + 4. Wire VQL-UT → VeriSimDB runtime bridge |
| 45 | + 5. Wire TypeLL → TypedQLiser for levels 5-10 |
| 46 | + 6. Wire PanLL TypeLL panel → running TypeLL server |
| 47 | + 7. Wire PanLL VQL panel → VQL-UT |
| 48 | + |
| 49 | +Round 3: Bring all → L5 (end-to-end):: |
| 50 | + 8. PanLL → TypeLL → VQL-UT → VeriSimDB pipeline test |
| 51 | + 9. TypedQLiser → TypeLL → VQL-UT type checking pipeline |
| 52 | + |
| 53 | +Round 4: Bring all → L6 (tested + benchmarked):: |
| 54 | + 10. Point-to-point tests for every connection |
| 55 | + 11. End-to-end tests for full pipelines |
| 56 | + 12. Aspect tests (error handling, edge cases, concurrency) |
| 57 | + 13. Benchmarks (latency, throughput, memory) |
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