risc-v.md

title	RISC-V

RISC-V

Digital Design and Computer Architecture, RISC-V Edition is nice book.

Links

• RISC-V Instruction Set Manual
• RISC-V Assembly Programmer's Manual
• rv8 - RISC-V simulator for x86-64. (HN)
• RISC-V Stumbling Blocks (2020)
• RISC-V Specification in Coq
• Formal Specification of RISC-V ISA in Kami
• RISC-V Software Ecosystem Overview
• Verified seL4 on secure RISC-V processors - Gernot Heiser (2020) (Paper) (HN) (Lobsters)
• SiFive - Design RISC-V CPUs in an hour. Get custom SoCs designed in weeks, not months.
• Rust on Risc-V (VexRiscv) on SpinalHDL with SymbiFlow on the Hackaday Supercon Badge (2020)
• vanadinite - RISC-V OS written in Rust.
• RISC-V Debug Specification
• Krste Asanović Videos
• Krste Asanović Publications
• riscv-rust - RISC-V processor emulator written in Rust.
• Sipeed Maixduino RISC-V board
• Learning embedded Rust by building RISC-V-powered robot (2020) (Lobsters)
• rvemu - RISC-V Online Emulataor.
• Overview of RISC-V Instruction Set Architecture
• RISC-V LLVM - Hosts a series of patches implementing a RISC-V backend for LLVM as well as initial tutorial material.
• lowRISC - Develop and maintain open source silicon designs and tools.
• RISC-V Assemly Language Programming book
• Bare metal RISC-V programming in Go (2020)
• Awesome RISC-V - Curated list of awesome RISC-V implementations.
• seL4 is verified on RISC-V! (2020) (Lobsters)
• RISC-V CPU - Open source CPU capable of booting Linux. (HN)
• Will RISC-V Revolutionize Computing? (Lobsters)
• Vulcan - RISC-V Instruction Set Simulator Built For Education.
• Ripes - Graphical processor simulator and assembly editor for the RISC-V ISA.
• SiFive Core IP 20G1 (HN)
• RISC-V from scratch (Code)
• PicoRio Linux RISC-V SBC is an open-source alternative to Raspberry Pi board (2020) (HN)
• PicoRV32 - Size-Optimized RISC-V CPU.
• SERV - Award-winning bit-serial RISC-V core.
• SweRVolf - FuseSoC-based SoC for the SweRV RISC-V core.
• mor1kx - OpenRISC 1000 processor IP core.
• RISC-V's Expanding Footprint (2020)
• Riding the RISC-V wave (2020) (HN)
• RIOS Lab - Developing open source IP and software that helps make the RISC-V ecosystem world-class.
• RISC-V: What’s Missing and Who’s Competing (2020) (HN)
• Bluespec - Open Source RISC-V Cores and Tools.
• Bluespec Compiler - Compiler, simulator, and tools for the Bluespec Hardware Description Language. (Contributed libraries and utilities)
• DANA - Chisel3 implementation of a fully connected neural network accelerator, DANA, supporting inference or learning.
• Writing a RISC-V Emulator from Scratch in 10 Steps
• Modernising RISC OS in 2020: is there hope for the ancient ARM OS? (2020) (Lobsters)
• Tockilator - Deducing Tock execution flows from Ibex Verilator traces.
• Lecture notes on RISC-V assembly (HN)
• narvie - Native REPL for RISC-V Instructions.
• OCaml RISC-V Extension
• Parsing RISC-V assembly (2020)
• RISC-V Core - 32-bit RISC-V core written in Verilog and an instruction set simulator supporting RV32IM.
• biRISC-V - 32-bit dual issue RISC-V CPU.
• Understanding Non-Local Jumps (setjmp/longjmp) in RISC-V Assembly (2020)
• Tinsel - RISC-V-based manythread message-passing architecture designed for FPGA clusters.
• Zip CPU - Small, light weight, RISC CPU soft core. (Web)
• ex-ARM engineer critiques RISC-V (HN)
• Precursor - Mobile, Open Hardware, RISC-V System-on-Chip (SoC) Development Kit. (Precursor: From Boot to Root)
• Dynamic Binary Translation (RISC-V -> x86) - Make RISC-V code executable on the x86-64 ISA by means of dynamic binary translation.
• Western Digital SweRV RISC-V Core (HN)
• RISC-V Cores and SoC Overview
• Getting Graphical Output from our Custom RISC-V Operating System in Rust (2020)
• Linux on LiteX-VexRiscv
• rvddt - RISC-V Dynamic Debugging Tool.
• Jonesforth RISC-V - RISC-V implementation of Jones forth.
• RISCV-DV - SV/UVM based open-source instruction generator for RISC-V processor verification.
• venus - RISC-V instruction set simulator built for education. (Code)
• RISC-V Reference Card (PDF)
• What do RISC and CISC mean in 2020? (HN)
• SERV - SErial RISC-V CPU.
• RISC-V Educational Materials
• Do Some ARM (2018)
• The Genius of RISC-V Microprocessors (2020) (Lobsters)
• Swimmer-RISCV - Instruction set simulator for RISC-V.
• Dydra - Instruction set emulator written in Rust, now supports RISC-V as guest ISA, x86-64 as host ISA.
• RSD - RISC-V Out-of-Order Superscalar Processor. (HN)
• v8-riscv - Port of JavaScript V8 engine to RISC-V. (HN)
• RISC-V isn't as interesting as you think (2021) (Lobsters) (HN)
• Rocket Chip Generator - Contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core.
• Designing a RISC-V CPU (2021) (HN)
• RISC-V assembler in Tcl
• RISC-V Getting Started Guide (Code)
• Lion: A formally verified, 5-stage pipeline RISC-V core (HN)
• R2VM - Rust RISC-V Virtual Machine.
• What happens when you load into x0 on RISC-V? (2021)
• RARS - RISC-V Assembler and Runtime Simulator.
• RustSBI - RISC-V Supervisor Binary Interface (SBI) implementation in Rust; runs on M-mode.
• Spike RISC-V ISA Simulator
• Examples of RISC-V Assembly Programs (HN)
• RISC-V ELF psABI Document - Processor-specific application binary interface document for RISC-V.
• riscv-mini - Simple RISC-V 3-stage pipeline written in Chisel.
• BlackParrot - Linux-Capable Accelerator Host RISC-V Multicore.
• Build a RISC-V CPU From Scratch (2021) (HN)
• NEORV32 RISC-V Processor - Size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL. (HN)
• RISC-V Adventures: Lightening (Part 2)
• RISC-V Supervisor Binary Interface Spec
• George Hotz | twitchcore: a little RISC-V core | in Python | in Verilog | on FPGA (2021)
• XiangShan - Open-source high-performance RISC-V processor.
• XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76 (2021) (HN)
• RISC-V Bytes
• RVVM - RISC-V Virtual Machine. (HN)
• seL4 Integrity Enforcement Proved for RISC-V (2021)
• VexRiscv, OpenOCD, and Traps (2021) (Code)
• Learning how to make RISC-V 32bit CPU with Chisel
• Linux in a Pixel Shader – A RISC-V Emulator for VRChat (2021) (HN)
• rvc - 32-bit RISC-V emulator in a shader (and C).
• Building a RISC-V CPU Core
• Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip (2021)
• RISC-V Cryptography Extension (HN)
• RISC-V Wiki (GitHub)
• Berkeley Out-of-Order Machine (BOOM - Synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language.
• HiFive Unmatched - RISC-V Linux development platform. (HN)
• RVirt - S-mode trap-and-emulate hypervisor for RISC-V.
• Vortex RISC-V GPGPU - Full-system RISCV-based GPGPU processor. (Web) (Tutorials) (HN)
• RISC-V: The New Architecture on the Block (HN)
• riscv - Low level access to RISC-V processors using Rust.
• Nios V – Intel's RISC-V Processor (HN)
• Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip (2021) (HN)
• RISC-V and the CPU Revolution, Yunsup Lee (2018)
• RISC-V CPU In TypeScript - YouTube
• High-Level Synthesis For RISC-V (2021) (HN)
• The Genius of the RISC-V Microprocessor - Erik Engheim (2021)
• RISC-V Open Source Supervisor Binary Interface (OpenSBI)
• RISC-V J Extension Specification - Instructions for JITs (HN)
• “RISC V is a terrible architecture” (2021) (HN)
• New SiFive RISC-V core P650 with 40% IPC increase (2021) (HN)
• XCrypto - Cryptographic ISE for RISC-V.
• MemPool - 256-RISC-V-core system with low-latency access into shared L1 memory.
• FPnew - Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
• ZeroSoC - RISC-V SoC designed to demonstrate the capabilities of SiliconCompiler.
• Understanding Assembly Part I: RISC-V (2021)
• RISC-V Summit 2021 - YouTube
• ChristmasSoc - Dual-core RISC-V SoC with JTAG, atomics, SDRAM.
• Beyond RISC – The Post-RISC Architecture (1996) (HN)
• SiFive-Core - Low level access to SiFive RISC-V processor cores.
• Minerva - 32-bit RISC-V soft processor.
• Fuxi - 32-bit pipelined RISC-V processor written in Chisel3.
• NERV - Naive Educational RISC V processor.
• YARI - High performance soft core RISC implementation, binary compatible with a subset of MIPS R3000.
• 32-bit RISC-V Emulator in Rust
• Steel - RISC-V processor core that implements the RV32I and Zicsr instruction sets of the RISC-V specifications.
• Sail RISC-V model - Formal specification of the RISC-V architecture, written in Sail.
• Ultra-Low Power RISC-V Core
• RISC-V Opcodes
• Piccolo - RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT).
• RISC-V-Computer built in Logisim capable of running C/C++ programs
• RISC-V Formal Verification Framework
• Qor - Simple kernel written in Rust for RISC-V.
• SRV32 - Simple 3-stage pipeline RISC-V processor.
• ZFS on a single core RISC-V hardware with 512MB (2022) (HN)
• RISC-V Guide
• RISC-V Architecture Test SIG
• Addressing Criticism of RISC-V Microprocessors (2022) (HN)
• RISC-V GNU Compiler Toolchain
• Cross-Compiling Rust for RISC-V (2022) (HN)
• Coffer - RISC-V Trusted Execution Environment.
• VRoom - High end RISC-V implementation. (HN) (Code)
• NaxRiscv - RISC-V core.
• YARVI - RISC-V Implementation.
• FlatRv - Cross-platform RISC-V interpreter that implements the RV32IMA instruction set.
• RISC-V Formal Verification Framework
• Flute - RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance.
• RISCV-ISA-Spec - Formal specification of RISC-V Instruction Set.
• Snitch System - Lean but mean RISC-V system.
• JavaScript RISC-V ISA Simulator. Boots Linux in a web-browser
• RVScript - Fast RISC-V-based scripting backend for game engines.
• Opening a UDP Socket in RISC-V Assembly (2022)
• RISC-V Torture Test
• SBI - Rust library to interface with the RISC-V Supervisor Binary Interface.
• RISC V Emulator
• riscv-rt - Minimal runtime / startup for RISC-V CPU's.
• RISC-V Toolchain Conventions
• ESP32-C5: Espressif’s First Dual-Band Wi-Fi 6 MCU (2022) (HN)
• RISC-V Is Getting MSIs (2022)
• Simple RISC V core for teaching
• RISC-V linker relaxation in lld (2022)
• ExperiarSoC - RISC-V SoC designed for the Efabless Open MPW Program.
• RudolV - RISC-V processor for real-time systems.
• RiftCore - 9-stage, single-issue, out of order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache system.
• Intro to GCC bootstrap in RISC-V (2022)
• PsPIN - RISC-V in-network accelerator for flexible high-performance low-power packet processing.
• Minimal operating system (2K LOC) on a small RISC-V board
• ztachip - RISCV accelerator for vision and AI edge applications running on low-end FPGA devices or custom ASIC.
• RISu064 - Dual-issue RV64IM processor for fun & learning.
• What's new for RISC-V in LLVM 15 (2022)
• Salus - Micro hypervisor for RISC-V systems.
• RISC-V Configuration Validator
• Ox64 is a RISC-V Linux-capable SBC for $8 (2022)
• RISCOF - RISC-V Architectural Test Framework.
• RISC In 2022 (Lobsters) (HN)
• TordBoyau - Pipelined RISC-V processor.
• The RISC Deprogrammer (2022) (HN)
• Minimax - Compressed-First, Microcoded RISC-V CPU. (HN)
• RISC-V Vector Autometic Tests Generator
• Computer Organization and Design RISC-V Edition (2017)
• Digital Design and Computer Architecture, RISC-V Edition (2021)
• Welcome to the First RISC-V Site (HN)
• Libriscv - RISC-V userspace emulator library. (HN)
• Tiny C header-only RISC-V emulator (HN) (Explained)
• Olympia - Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model.