OpenVAF is neat.
- Verilog HDL and its ancestors and descendants (2020)
- Various HDL (Verilog) IP Cores
- Generic Piplined FFT Core Generator - Configurable C++ generator of pipelined Verilog FFT cores.
- Simple, basic, formally verified UART controller
- SymbiFlow - Open source toolchain for the development of FPGAs of multiple vendors. (GitHub)
- Verilog PCI Express Components
- Verilog AXI Components
- Verilator - Fastest Verilog/SystemVerilog simulator. (Web)
- YosysHQ - Team maintaining Yosys and the related Open Source EDA projects. (GitHub)
- Yosys - Framework for Verilog RTL synthesis. (Web)
- Icarus Verilog - Verilog simulation and synthesis tool. (Code)
- Factorio Verilog Compiler - Compile Verilog (a hardware description language) into Factorio blueprints. (HN)
- Clash - Haskell to VHDL/Verilog/SystemVerilog compiler. (Web)
- sv2v - SystemVerilog to Verilog conversion.
- CXXRTL, a Yosys Simulation Backend (2020) (Code)
- Wyre - Hardware definition language that compiles to Verilog.
- Verilog Ethernet Components - Verilog Ethernet components for FPGA implementation.
- Verilog Simulation with Verilator and SDL (2021) (HN)
- IceChips - Library of all common discrete logic devices in Verilog.
- Verilog Format - Verilog formatter.
- Verilog AST (VAST) - Rust library for building and manipulating Verilog ASTs.
- Open Source Verification Bundle (OSVB) - Gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. (Docs)
- Rethinking floating point for deep learning (2018) (Code)
- SPU32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog.
- Verilog to Routing (VTR) - Open Source CAD Flow for FPGA Research.
- gplgpu - 2D/3D graphics engine in verilog.
- svls - SystemVerilog language server.
- Verilog grammar for tree-sitter
- HDL Reference Designs
- Caravel Harness - Standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
- Verilog Is Weird (HN)
- Asynchronous dual clock FIFO - Dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog.
- VHDL grammar for tree-sitter
- IOb-cache - High-performance configurable open-source Verilog cache.
- VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA.
- Asicle - Wordle implemented in Verilog.
- Verilog rules for Bazel
- cocotb - Open source coroutine-based cosimulation testbench environment for verifying VHDL and SystemVerilog RTL using Python. (Web)
- Tutorial on building your own CPU, in Verilog
- OH! - Verilog library for ASIC and FPGA designers.
- Metron C++ to Verilog Tutorial
- OpenVAF - Modern VerilogA compiler focused on compact modelling.
- Veriloggen - Mixed-Paradigm Hardware Construction Framework.
- OpenOFDM - Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
- sv2chisel - Verilog to Chisel translator.
- libvhdl - Library of reusable VHDL components.
- psl_with_ghdl - Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys).
- formal_hw_verification - Trying to verify Verilog/VHDL designs with formal methods and tools.
- cryptocores - Cryptography IP-cores & tests written in VHDL / Verilog.
- GHDL - Open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL.
- OpenLane - Automated RTL to GDSII flow based on several components.
- OpenROAD - Integrated chip physical design tool that takes a design from synthesized Verilog to routed layout.
- OpenCGRA - Open-source framework for modeling, testing, and evaluating CGRAs.
- SystemVerilog support for Yosys
- OpenVAF - Verilog-A compiler that can compile Verilog-A files for use in circuit simulator.
- bsg_manycore - Tile based architecture designed for computing efficiency, scalability and generality.
- Verilog-Perl - Verilog parser, preprocessor, and related tools.
- TinyTapeout - Educational project that makes it easier and cheaper than ever to get your digital designs manufactured on a real chip.