fix(virtio/mem): reject BAR regions overlapping TD private DRAM

Virtio PCI capability parsing built MemoryRegion instances directly from
BAR base, offset, and length values, all of which are controlled by the
untrusted VMM. MemoryRegion::new only guarded against integer overflow
and never compared the resulting [base, base + length) range against the
TD's private DRAM. A malicious host could therefore program a BAR so that
a common/notify/device-config region or the MSI-X table pointed into
guest-private memory. In a cfg(not(tdcall)) build the subsequent
read/write_volatile would then read or corrupt TD-private secrets
(INV-4 / RC-066).

Add region_overlaps_private_dram() in the pci crate, which uses the
existing E820 memory map to detect overlap with platform RAM and rejects
any region below 1 MiB. Enforce it in MemoryRegion::new so that all four
BAR-derived call sites in VirtioPciTransport::init fail closed with
VirtioError::InvalidParameter. The check is purely arithmetic and applies
regardless of the tdcall feature; it is skipped only under the fuzz
feature, which is not a security boundary.

Signed-off-by: Michal Tarnacki <michal.tarnacki@intel.com>
Co-authored-by: GitHub Copilot <noreply@github.com>

Author: 2 people

src/devices/pci/src/mmio.rs

@@ -38,6 +38,39 @@ pub fn init_mmio() {
     *MMIO64.lock() = MMIO64_START;
 }
 
+/// Device MMIO is never allowed to live below 1 MiB. That range is reserved
+/// for legacy low memory and is not a valid MMIO aperture.
+pub const MMIO_LOW_LIMIT: u64 = 0x10_0000;
+
+/// Returns `true` if `[base, base + length)` hits RAM or the low 1 MiB.
+/// Defense in depth for host-controlled BARs.
+pub fn region_overlaps_private_dram(base: u64, length: u64) -> bool {
+    let end = match base.checked_add(length) {
+        Some(end) => end,
+        None => return true,
+    };
+
+    if base < MMIO_LOW_LIMIT {
+        return true;
+    }
+
+    let memory_map = MEMORY_MAP.lock();
+    for region in memory_map.iter() {
+        let region_end = match region.addr.checked_add(region.size) {
+            Some(region_end) => region_end,
+            None => return true,
+        };
+
+        // Overlap test for the half-open intervals [base, end) and
+        // [region.addr, region_end).
+        if base < region_end && end > region.addr {
+            return true;
+        }
+    }
+
+    false
+}
+
 #[cfg(feature = "fuzz")]
 pub fn alloc_mmio32(size: u32) -> Result<u32> {
     let cur = *MMIO_OFFSET.lock();

src/devices/virtio/src/mem.rs

@@ -33,6 +33,12 @@ impl MemoryRegion {
     pub fn new(base: u64, length: u64) -> Option<MemoryRegion> {
         let _ = base.checked_add(length)?;
 
+        // Reject host-controlled BARs that hit private DRAM or the low 1 MiB.
+        #[cfg(not(feature = "fuzz"))]
+        if pci::region_overlaps_private_dram(base, length) {
+            return None;
+        }
+
         Some(MemoryRegion { base, length })
     }