Drop SIMD32 to SIMD16 on non-VRT XE2 over GRF budget

Extend the early SIMD16-drop heuristic to non-VRT XE2 platforms: drop SIMD32 to
SIMD16 when its register-pressure estimate exceeds the GRF budget. The drop is
controlled by the existing AllowSIMD16DropForXE2Plus switch; the redundant
AllowEarlySIMD16DropForXE3 flag is removed.

Author: agrabezh

IGC/Compiler/CISACodeGen/OpenCLKernelCodeGen.cpp

@@ -2601,7 +2601,21 @@ static bool shouldDropToSIMD16(uint32_t maxPressure, uint32_t simd16Pressure, ui
   if (simdMode != SIMDMode::SIMD32 || !isEntryFunc(pMdUtils, F)) {
     return false;
   }
-  if (!pCtx->isAutoGRFSelectionEnabled() || pCtx->getNumGRFPerThread(false) != 0) {
+
+  bool autoGRF = pCtx->isAutoGRFSelectionEnabled();
+
+  // Non-VRT platforms have no VRT GRF step-up: SIMD32 is only profitable when
+  // its register pressure fits the GRF budget. Drop to SIMD16 when SIMD32
+  // pressure exceeds the budget -- the forced GRF count, otherwise 128 (256 in
+  // auto large-GRF mode).
+  if (pCtx->platform.isCoreXE2()) {
+    uint32_t grfBudget = pCtx->getNumGRFPerThread(false);
+    if (grfBudget == 0)
+      grfBudget = autoGRF ? 256 : 128;
+    return simd32Pressure > grfBudget;
+  }
+
+  if (!autoGRF || pCtx->getNumGRFPerThread(false) != 0) {
     return false;
   }
 
@@ -2729,7 +2743,8 @@ SIMDStatus COpenCLKernel::checkSIMDCompileCondsForMin16(SIMDMode simdMode, EmitP
     }
   }
 
-  if (EP.m_canAbortOnSpill && pCtx->platform.isCoreXE3() && IGC_IS_FLAG_ENABLED(AllowEarlySIMD16DropForXE3)) {
+  bool isSupportedCore = pCtx->platform.isCoreXE2() || pCtx->platform.isCoreXE3();
+  if (EP.m_canAbortOnSpill && isSupportedCore && IGC_IS_FLAG_ENABLED(AllowSIMD16DropForXE2Plus)) {
     uint32_t simd16Pressure = getMaxPressureForSIMD(F, numLanes(SIMDMode::SIMD16));
     uint32_t simd32Pressure = getMaxPressureForSIMD(F, numLanes(SIMDMode::SIMD32));
     bool shouldDrop = shouldDropToSIMD16(maxPressure, simd16Pressure, simd32Pressure, simdMode, pCtx, pMdUtils, &F);

IGC/common/igc_flags.h

@@ -1636,8 +1636,8 @@ DECLARE_IGC_REGKEY(bool, VectorizerLog, false, "Dump Vectorizer Log, usefull for
 DECLARE_IGC_REGKEY(bool, VectorizerLogToErr, false, "Dump Vectorizer Log to stdErr", true)
 DECLARE_IGC_REGKEY(bool, EnableReusingXYZWStoreConstPayload, true, "Enable reusing XYZW stores const payload", false)
 DECLARE_IGC_REGKEY(bool, EnableReusingLSCStoreConstPayload, false, "Enable reusing LSC stores const payload", false)
-DECLARE_IGC_REGKEY(bool, AllowSIMD16DropForXE2Plus, true, "Controls the switch for XE2 and XE3 simd16 drop", false)
-DECLARE_IGC_REGKEY(bool, AllowEarlySIMD16DropForXE3, true, "Controls the early drop to simd16 for XE3", false)
+DECLARE_IGC_REGKEY(bool, AllowSIMD16DropForXE2Plus, true,
+                   "Controls the switch for XE2 and XE3 simd16 drop, including the early RPE-based drop", false)
 DECLARE_IGC_REGKEY(DWORD, EarlySIMD16DropForXE3Threshold, 256, "Threshold for the early drop to simd16 for XE3", false)
 DECLARE_IGC_REGKEY(DWORD, OCLVRTSimd16DropSimd32High, 160,
                    "Drop SIMD32 to SIMD16 on VRT platforms when SIMD32 RPE exceeds this value", false)

documentation/configuration_flags.md

@@ -683,10 +683,9 @@ $ export IGC_ShaderDumpEnable=1
 | `AllocateZeroInitializedVarsInBss` | Allocate zero initialized global variables in .bss section in ZEBinary | Available |
 | `AllowConstMadOpMovToReg` | Enable matching of mad instruction if constant greater than 16-bits. This will generate a mov in                   vISA for the constant operand due to it not fitting as an imm16 operand. At this point, the                   generated asm likely will fall back onto mul+add for the main case where src1 is the constant | - |
 | `AllowCrossBlockMatchMad` | Enable cross basic block matching of mad instructions. This may lead to increased register                   pressure, but in exchange, may reduce instruction count | - |
-| `AllowEarlySIMD16DropForXE3` | Controls the early drop to simd16 for XE3 | - |
 | `AllowMultipleMulUsesMatchMad` | Enable a multiply instruction with multiple uses to be matched to a mad instruction. This essentially forces the    recalculation of the intermediate multiply result for every potential mad instruction, which will have    performance impacts but may reduce instruction count and register pressure in case both mul operands need to be    live past the add/sub but the intermediate mul result does not. | - |
 | `AllowNonLoopConstantPromotion` | Allows promotion for constants not in loop (e.g. used once) | - |
-| `AllowSIMD16DropForXE2Plus` | Controls the switch for XE2 and XE3 simd16 drop | - |
+| `AllowSIMD16DropForXE2Plus` | Controls the switch for XE2 and XE3 simd16 drop, including the early RPE-based drop | - |
 | `AllowStackCallRetry` | Enable/Disable retry when stack function spill. 0 - Don't allow, 1 - Allow retry on kernel group,                   2 - Allow retry per function | - |
 | `BlockFrequencySampling` | Use block frequencies to derive a distribution | Available |
 | `ByPassAllocaSizeHeuristic` | Force some Alloca to pass the pressure heuristic until the given size | Available |