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[AMDGPU] Make v2f32 legal for G_FNEG and G_FABS and pattern update (#195419)
 G_FNEG and G_FABS were made legal for v2f32 when packed fp32 instructions were implemented. For some unknown reasons, this legalization was not upstreamed yet. This work makes v2f32 legal for G_FNEG and G_FABS, and updates a few tablegen patterns to ensure instructions can be correctly selected.
1 parent 5d98710 commit 8ee61ad

4 files changed

Lines changed: 284 additions & 25 deletions

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‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1030,11 +1030,13 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
10301030
.scalarize(0)
10311031
.clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64);
10321032

1033-
getActionDefinitionsBuilder({G_FNEG, G_FABS})
1034-
.legalFor(FPTypesPK16)
1035-
.clampMaxNumElementsStrict(0, S16, 2)
1036-
.scalarize(0)
1037-
.clampScalar(0, S16, S64);
1033+
auto &FNegAbs = getActionDefinitionsBuilder({G_FNEG, G_FABS});
1034+
FNegAbs.legalFor(FPTypesPK16)
1035+
.legalFor(ST.hasPackedFP32Ops(), {V2S32})
1036+
.clampMaxNumElementsStrict(0, S16, 2);
1037+
if (ST.hasPackedFP32Ops())
1038+
FNegAbs.clampMaxNumElementsStrict(0, S32, 2);
1039+
FNegAbs.scalarize(0).clampScalar(0, S16, S64);
10381040

10391041
if (ST.has16BitInsts()) {
10401042
getActionDefinitionsBuilder(G_FSQRT)

‎llvm/lib/Target/AMDGPU/SIInstructions.td‎

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2139,32 +2139,43 @@ def : GCNPat <
21392139
def : GCNPat <
21402140
(UniformUnaryFrag<fneg> (v2f32 SReg_64:$src)),
21412141
(v2f32 (REG_SEQUENCE SReg_64,
2142-
(f32 (COPY_TO_REGCLASS (S_XOR_B32 (i32 (EXTRACT_SUBREG $src, sub0)),
2142+
(f32 (COPY_TO_REGCLASS (S_XOR_B32 (i32 (EXTRACT_SUBREG SReg_64:$src, sub0)),
21432143
(i32 (S_MOV_B32 (i32 0x80000000)))),
21442144
SReg_32)), sub0,
2145-
(f32 (COPY_TO_REGCLASS (S_XOR_B32 (i32 (EXTRACT_SUBREG $src, sub1)),
2145+
(f32 (COPY_TO_REGCLASS (S_XOR_B32 (i32 (EXTRACT_SUBREG SReg_64:$src, sub1)),
21462146
(i32 (S_MOV_B32 (i32 0x80000000)))),
21472147
SReg_32)), sub1))
21482148
>;
21492149

21502150
def : GCNPat <
21512151
(UniformUnaryFrag<fabs> (v2f32 SReg_64:$src)),
21522152
(v2f32 (REG_SEQUENCE SReg_64,
2153-
(f32 (COPY_TO_REGCLASS (S_AND_B32 (i32 (EXTRACT_SUBREG $src, sub0)),
2153+
(f32 (COPY_TO_REGCLASS (S_AND_B32 (i32 (EXTRACT_SUBREG SReg_64:$src, sub0)),
21542154
(i32 (S_MOV_B32 (i32 0x7fffffff)))),
21552155
SReg_32)), sub0,
2156-
(f32 (COPY_TO_REGCLASS (S_AND_B32 (i32 (EXTRACT_SUBREG $src, sub1)),
2156+
(f32 (COPY_TO_REGCLASS (S_AND_B32 (i32 (EXTRACT_SUBREG SReg_64:$src, sub1)),
21572157
(i32 (S_MOV_B32 (i32 0x7fffffff)))),
21582158
SReg_32)), sub1))
21592159
>;
21602160

2161+
def : GCNPat <
2162+
(DivergentUnaryFrag<fabs> (v2f32 VReg_64:$src)),
2163+
(v2f32 (REG_SEQUENCE VReg_64,
2164+
(f32 (COPY_TO_REGCLASS (V_AND_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$src, sub0)),
2165+
(i32 (S_MOV_B32 (i32 0x7fffffff)))),
2166+
VGPR_32)), sub0,
2167+
(f32 (COPY_TO_REGCLASS (V_AND_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$src, sub1)),
2168+
(i32 (S_MOV_B32 (i32 0x7fffffff)))),
2169+
VGPR_32)), sub1))
2170+
>;
2171+
21612172
def : GCNPat <
21622173
(UniformUnaryFrag<fneg> (fabs (v2f32 SReg_64:$src))),
21632174
(v2f32 (REG_SEQUENCE SReg_64,
2164-
(f32 (COPY_TO_REGCLASS (S_OR_B32 (i32 (EXTRACT_SUBREG $src, sub0)),
2175+
(f32 (COPY_TO_REGCLASS (S_OR_B32 (i32 (EXTRACT_SUBREG SReg_64:$src, sub0)),
21652176
(i32 (S_MOV_B32 (i32 0x80000000)))),
21662177
SReg_32)), sub0,
2167-
(f32 (COPY_TO_REGCLASS (S_OR_B32 (i32 (EXTRACT_SUBREG $src, sub1)),
2178+
(f32 (COPY_TO_REGCLASS (S_OR_B32 (i32 (EXTRACT_SUBREG SReg_64:$src, sub1)),
21682179
(i32 (S_MOV_B32 (i32 0x80000000)))),
21692180
SReg_32)), sub1))
21702181
>;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll‎

Lines changed: 4 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -911,15 +911,9 @@ define void @v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_uni(<2 x float> in
911911
; GFX942-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_uni:
912912
; GFX942: ; %bb.0:
913913
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
914-
; GFX942-NEXT: v_mov_b32_e32 v2, s0
915-
; GFX942-NEXT: v_mov_b32_e32 v3, s1
916-
; GFX942-NEXT: v_mov_b32_e32 v4, s2
917-
; GFX942-NEXT: v_mov_b32_e32 v5, s3
918-
; GFX942-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
919-
; GFX942-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
920-
; GFX942-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
921-
; GFX942-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
922-
; GFX942-NEXT: v_pk_fma_f32 v[2:3], v[2:3], v[4:5], s[16:17]
914+
; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
915+
; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[16:17]
916+
; GFX942-NEXT: v_pk_fma_f32 v[2:3], s[0:1], v[2:3], v[4:5] neg_lo:[1,1,0] neg_hi:[1,1,0]
923917
; GFX942-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
924918
; GFX942-NEXT: s_waitcnt vmcnt(0)
925919
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -982,11 +976,7 @@ define void @v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_div(<2 x float> %x
982976
; GFX942-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_div:
983977
; GFX942: ; %bb.0:
984978
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
985-
; GFX942-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
986-
; GFX942-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
987-
; GFX942-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
988-
; GFX942-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
989-
; GFX942-NEXT: v_pk_fma_f32 v[0:1], v[0:1], v[2:3], v[4:5]
979+
; GFX942-NEXT: v_pk_fma_f32 v[0:1], v[0:1], v[2:3], v[4:5] neg_lo:[1,1,0] neg_hi:[1,1,0]
990980
; GFX942-NEXT: global_store_dwordx2 v[6:7], v[0:1], off
991981
; GFX942-NEXT: s_waitcnt vmcnt(0)
992982
; GFX942-NEXT: s_setpc_b64 s[30:31]

‎llvm/test/CodeGen/AMDGPU/fneg-fabs-v2f32.ll‎

Lines changed: 256 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,256 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90A,GFX90A-SDAG %s
3+
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90A,GFX90A-GISEL %s
4+
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950,GFX950-SDAG %s
5+
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL %s
6+
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
7+
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
8+
9+
define <2 x float> @fneg_v2f32_v(<2 x float> %first) {
10+
; GFX90A-LABEL: fneg_v2f32_v:
11+
; GFX90A: ; %bb.0: ; %bb
12+
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
13+
; GFX90A-NEXT: v_pk_add_f32 v[0:1], v[0:1], 0 neg_lo:[1,1] neg_hi:[1,1]
14+
; GFX90A-NEXT: s_setpc_b64 s[30:31]
15+
;
16+
; GFX950-LABEL: fneg_v2f32_v:
17+
; GFX950: ; %bb.0: ; %bb
18+
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
19+
; GFX950-NEXT: v_pk_add_f32 v[0:1], v[0:1], 0 neg_lo:[1,1] neg_hi:[1,1]
20+
; GFX950-NEXT: s_setpc_b64 s[30:31]
21+
;
22+
; GFX1250-LABEL: fneg_v2f32_v:
23+
; GFX1250: ; %bb.0: ; %bb
24+
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
25+
; GFX1250-NEXT: s_wait_kmcnt 0x0
26+
; GFX1250-NEXT: v_pk_add_f32 v[0:1], v[0:1], 0 neg_lo:[1,1] neg_hi:[1,1]
27+
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
28+
bb:
29+
%neg = fneg <2 x float> %first
30+
ret <2 x float> %neg
31+
}
32+
33+
define <2 x float> @fabs_v2f32_v(<2 x float> %first) {
34+
; GFX90A-SDAG-LABEL: fabs_v2f32_v:
35+
; GFX90A-SDAG: ; %bb.0: ; %bb
36+
; GFX90A-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
37+
; GFX90A-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
38+
; GFX90A-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
39+
; GFX90A-SDAG-NEXT: s_setpc_b64 s[30:31]
40+
;
41+
; GFX90A-GISEL-LABEL: fabs_v2f32_v:
42+
; GFX90A-GISEL: ; %bb.0: ; %bb
43+
; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
44+
; GFX90A-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
45+
; GFX90A-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
46+
; GFX90A-GISEL-NEXT: s_setpc_b64 s[30:31]
47+
;
48+
; GFX950-SDAG-LABEL: fabs_v2f32_v:
49+
; GFX950-SDAG: ; %bb.0: ; %bb
50+
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
51+
; GFX950-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
52+
; GFX950-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
53+
; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
54+
;
55+
; GFX950-GISEL-LABEL: fabs_v2f32_v:
56+
; GFX950-GISEL: ; %bb.0: ; %bb
57+
; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
58+
; GFX950-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
59+
; GFX950-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
60+
; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
61+
;
62+
; GFX1250-LABEL: fabs_v2f32_v:
63+
; GFX1250: ; %bb.0: ; %bb
64+
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
65+
; GFX1250-NEXT: s_wait_kmcnt 0x0
66+
; GFX1250-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
67+
; GFX1250-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
68+
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
69+
bb:
70+
%abs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %first)
71+
ret <2 x float> %abs
72+
}
73+
74+
define <2 x float> @fneg_fabs_v2f32_v(<2 x float> %first) {
75+
; GFX90A-LABEL: fneg_fabs_v2f32_v:
76+
; GFX90A: ; %bb.0: ; %bb
77+
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
78+
; GFX90A-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
79+
; GFX90A-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
80+
; GFX90A-NEXT: v_pk_add_f32 v[0:1], v[0:1], 0 neg_lo:[1,1] neg_hi:[1,1]
81+
; GFX90A-NEXT: s_setpc_b64 s[30:31]
82+
;
83+
; GFX950-LABEL: fneg_fabs_v2f32_v:
84+
; GFX950: ; %bb.0: ; %bb
85+
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
86+
; GFX950-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
87+
; GFX950-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
88+
; GFX950-NEXT: v_pk_add_f32 v[0:1], v[0:1], 0 neg_lo:[1,1] neg_hi:[1,1]
89+
; GFX950-NEXT: s_setpc_b64 s[30:31]
90+
;
91+
; GFX1250-LABEL: fneg_fabs_v2f32_v:
92+
; GFX1250: ; %bb.0: ; %bb
93+
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
94+
; GFX1250-NEXT: s_wait_kmcnt 0x0
95+
; GFX1250-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
96+
; GFX1250-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
97+
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
98+
; GFX1250-NEXT: v_pk_add_f32 v[0:1], v[0:1], 0 neg_lo:[1,1] neg_hi:[1,1]
99+
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
100+
bb:
101+
%abs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %first)
102+
%neg = fneg <2 x float> %abs
103+
ret <2 x float> %neg
104+
}
105+
106+
define <2 x float> @fneg_v2f32_s(<2 x float> inreg %first) {
107+
; GFX90A-LABEL: fneg_v2f32_s:
108+
; GFX90A: ; %bb.0: ; %bb
109+
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
110+
; GFX90A-NEXT: s_xor_b32 s4, s17, 0x80000000
111+
; GFX90A-NEXT: s_xor_b32 s5, s16, 0x80000000
112+
; GFX90A-NEXT: v_mov_b32_e32 v0, s5
113+
; GFX90A-NEXT: v_mov_b32_e32 v1, s4
114+
; GFX90A-NEXT: s_setpc_b64 s[30:31]
115+
;
116+
; GFX950-LABEL: fneg_v2f32_s:
117+
; GFX950: ; %bb.0: ; %bb
118+
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
119+
; GFX950-NEXT: s_xor_b32 s1, s1, 0x80000000
120+
; GFX950-NEXT: s_xor_b32 s0, s0, 0x80000000
121+
; GFX950-NEXT: v_mov_b32_e32 v0, s0
122+
; GFX950-NEXT: v_mov_b32_e32 v1, s1
123+
; GFX950-NEXT: s_setpc_b64 s[30:31]
124+
;
125+
; GFX1250-LABEL: fneg_v2f32_s:
126+
; GFX1250: ; %bb.0: ; %bb
127+
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
128+
; GFX1250-NEXT: s_wait_kmcnt 0x0
129+
; GFX1250-NEXT: s_xor_b32 s0, s0, 0x80000000
130+
; GFX1250-NEXT: s_xor_b32 s1, s1, 0x80000000
131+
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
132+
; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
133+
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
134+
bb:
135+
%neg = fneg <2 x float> %first
136+
ret <2 x float> %neg
137+
}
138+
139+
define <2 x float> @fabs_v2f32_s(<2 x float> inreg %first) {
140+
; GFX90A-SDAG-LABEL: fabs_v2f32_s:
141+
; GFX90A-SDAG: ; %bb.0: ; %bb
142+
; GFX90A-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
143+
; GFX90A-SDAG-NEXT: s_bitset0_b32 s16, 31
144+
; GFX90A-SDAG-NEXT: s_bitset0_b32 s17, 31
145+
; GFX90A-SDAG-NEXT: v_mov_b32_e32 v0, s16
146+
; GFX90A-SDAG-NEXT: v_mov_b32_e32 v1, s17
147+
; GFX90A-SDAG-NEXT: s_setpc_b64 s[30:31]
148+
;
149+
; GFX90A-GISEL-LABEL: fabs_v2f32_s:
150+
; GFX90A-GISEL: ; %bb.0: ; %bb
151+
; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
152+
; GFX90A-GISEL-NEXT: s_and_b32 s4, s17, 0x7fffffff
153+
; GFX90A-GISEL-NEXT: s_and_b32 s5, s16, 0x7fffffff
154+
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v0, s5
155+
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v1, s4
156+
; GFX90A-GISEL-NEXT: s_setpc_b64 s[30:31]
157+
;
158+
; GFX950-SDAG-LABEL: fabs_v2f32_s:
159+
; GFX950-SDAG: ; %bb.0: ; %bb
160+
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
161+
; GFX950-SDAG-NEXT: s_bitset0_b32 s0, 31
162+
; GFX950-SDAG-NEXT: s_bitset0_b32 s1, 31
163+
; GFX950-SDAG-NEXT: v_mov_b32_e32 v0, s0
164+
; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, s1
165+
; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
166+
;
167+
; GFX950-GISEL-LABEL: fabs_v2f32_s:
168+
; GFX950-GISEL: ; %bb.0: ; %bb
169+
; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
170+
; GFX950-GISEL-NEXT: s_bitset0_b32 s1, 31
171+
; GFX950-GISEL-NEXT: s_bitset0_b32 s0, 31
172+
; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, s0
173+
; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, s1
174+
; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
175+
;
176+
; GFX1250-LABEL: fabs_v2f32_s:
177+
; GFX1250: ; %bb.0: ; %bb
178+
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
179+
; GFX1250-NEXT: s_wait_kmcnt 0x0
180+
; GFX1250-NEXT: s_bitset0_b32 s0, 31
181+
; GFX1250-NEXT: s_bitset0_b32 s1, 31
182+
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
183+
; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
184+
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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bb:
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%abs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %first)
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ret <2 x float> %abs
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}
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define <2 x float> @fneg_fabs_v2f32_s(<2 x float> inreg %first) {
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; GFX90A-SDAG-LABEL: fneg_fabs_v2f32_s:
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; GFX90A-SDAG: ; %bb.0: ; %bb
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; GFX90A-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-SDAG-NEXT: s_bitset0_b32 s17, 31
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; GFX90A-SDAG-NEXT: s_bitset0_b32 s16, 31
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; GFX90A-SDAG-NEXT: s_xor_b32 s4, s17, 0x80000000
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; GFX90A-SDAG-NEXT: s_xor_b32 s5, s16, 0x80000000
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; GFX90A-SDAG-NEXT: v_mov_b32_e32 v0, s5
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; GFX90A-SDAG-NEXT: v_mov_b32_e32 v1, s4
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; GFX90A-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX90A-GISEL-LABEL: fneg_fabs_v2f32_s:
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; GFX90A-GISEL: ; %bb.0: ; %bb
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; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-GISEL-NEXT: s_or_b32 s4, s17, 0x80000000
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; GFX90A-GISEL-NEXT: s_or_b32 s5, s16, 0x80000000
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; GFX90A-GISEL-NEXT: v_mov_b32_e32 v0, s5
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; GFX90A-GISEL-NEXT: v_mov_b32_e32 v1, s4
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; GFX90A-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX950-SDAG-LABEL: fneg_fabs_v2f32_s:
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; GFX950-SDAG: ; %bb.0: ; %bb
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; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX950-SDAG-NEXT: s_bitset0_b32 s1, 31
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; GFX950-SDAG-NEXT: s_bitset0_b32 s0, 31
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; GFX950-SDAG-NEXT: s_xor_b32 s1, s1, 0x80000000
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; GFX950-SDAG-NEXT: s_xor_b32 s0, s0, 0x80000000
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; GFX950-SDAG-NEXT: v_mov_b32_e32 v0, s0
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; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, s1
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; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX950-GISEL-LABEL: fneg_fabs_v2f32_s:
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; GFX950-GISEL: ; %bb.0: ; %bb
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; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX950-GISEL-NEXT: s_bitset1_b32 s1, 31
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; GFX950-GISEL-NEXT: s_bitset1_b32 s0, 31
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; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, s0
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; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, s1
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; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1250-SDAG-LABEL: fneg_fabs_v2f32_s:
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; GFX1250-SDAG: ; %bb.0: ; %bb
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; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
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; GFX1250-SDAG-NEXT: s_bitset0_b32 s0, 31
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; GFX1250-SDAG-NEXT: s_bitset0_b32 s1, 31
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; GFX1250-SDAG-NEXT: s_xor_b32 s0, s0, 0x80000000
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; GFX1250-SDAG-NEXT: s_xor_b32 s1, s1, 0x80000000
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; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-GISEL-LABEL: fneg_fabs_v2f32_s:
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; GFX1250-GISEL: ; %bb.0: ; %bb
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; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX1250-GISEL-NEXT: s_bitset1_b32 s0, 31
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; GFX1250-GISEL-NEXT: s_bitset1_b32 s1, 31
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
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bb:
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%abs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %first)
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%neg = fneg <2 x float> %abs
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ret <2 x float> %neg
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}

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