@@ -107,8 +107,6 @@ inline void fillEntry(TopologyEntry & entry, const uint32 & smtMaskWidth, const
107107 entry.socket_unique_core_id = entry.core_id ;
108108}
109109
110- #ifndef USER_KERNEL_SHARED
111-
112110inline bool initCoreMasks (uint32 & smtMaskWidth, uint32 & coreMaskWidth, uint32 & l2CacheMaskShift, uint32 & l3CacheMaskShift)
113111{
114112 // init constants for CPU topology leaf 0xB
@@ -170,7 +168,10 @@ inline bool initCoreMasks(uint32 & smtMaskWidth, uint32 & coreMaskWidth, uint32
170168 {
171169 l2CacheMaskShift++;
172170 }
171+
172+ #ifndef USER_KERNEL_SHARED
173173 DBG (1 , " Number of threads sharing L2 cache = " , threadsSharingL2, " [the most significant bit = " , l2CacheMaskShift , " ]" );
174+ #endif
174175
175176 uint32 threadsSharingL3 = 0 ;
176177 uint32 l3CacheMaskWidth = 0 ;
@@ -182,7 +183,11 @@ inline bool initCoreMasks(uint32 & smtMaskWidth, uint32 & coreMaskWidth, uint32
182183 {
183184 l3CacheMaskShift++;
184185 }
186+
187+ #ifndef USER_KERNEL_SHARED
185188 DBG (1 , " Number of threads sharing L3 cache = " , threadsSharingL3, " [the most significant bit = " , l3CacheMaskShift , " ]" );
189+ #endif
190+
186191 // Validate l3CacheMaskShift and ensure the bit range is correct
187192 if (l3CacheMaskShift > 31 )
188193 {
@@ -217,14 +222,16 @@ inline bool initCoreMasks(uint32 & smtMaskWidth, uint32 & coreMaskWidth, uint32
217222 {
218223 CacheMaskShift++;
219224 }
225+
226+ #ifndef USER_KERNEL_SHARED
220227 DBG (1 , " Max number of threads sharing L" , level , " " , cacheTypeStr , " cache = " , threadsSharingCache, " [the most significant bit = " , CacheMaskShift , " ]" ,
221228 " shift = " , CacheMaskShift);
229+ #endif
222230 ++it;
223231 }
224232 }
225233 return true ;
226234}
227- #endif
228235
229236}
230237
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