Fix regression: Adjust vendor name in MSR modules

dedekind · dedekind · commit 48cfe009aa96 · 2026-01-26T13:32:00.000Z
Signed-off-by: Artem Bityutskiy &lt;artem.bityutskiy@linux.intel.com&gt;
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -6,6 +6,7 @@ Versioning practices: [Semantic Versioning](https://semver.org/spec/v2.0.0.html)
 ## [ADD NEW VERSION HERE] - ADD DATE HERE
 ### Fixed
  - pepc tpmi * --base: Do not fail when 'tpmi_info' feature (0x81) is missing.
+ - pepc: Fix regression in 1.6.19: MSR modules did not work.
 ### Added
 ### Removed
 ### Changed
diff --git a/pepclibs/msr/EnergyPerfBias.py b/pepclibs/msr/EnergyPerfBias.py
@@ -57,7 +57,7 @@ class EnergyPerfBias(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_ENERGY_PERF_BIAS
     regname = "MSR_ENERGY_PERF_BIAS"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/FSBFreq.py b/pepclibs/msr/FSBFreq.py
@@ -126,7 +126,7 @@ class FSBFreq(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_FSB_FREQ
     regname = "MSR_FSB_FREQ"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/HWPCapabilities.py b/pepclibs/msr/HWPCapabilities.py
@@ -80,7 +80,7 @@ class HWPCapabilities(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_HWP_CAPABILITIES
     regname = "MSR_HWP_CAPABILITIES"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/HWPRequest.py b/pepclibs/msr/HWPRequest.py
@@ -124,7 +124,7 @@ class HWPRequest(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_HWP_REQUEST
     regname = "MSR_HWP_REQUEST"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/HWPRequestPkg.py b/pepclibs/msr/HWPRequestPkg.py
@@ -73,7 +73,7 @@ class HWPRequestPkg(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_HWP_REQUEST_PKG
     regname = "MSR_HWP_REQUEST_PKG"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/PCStateConfigCtl.py b/pepclibs/msr/PCStateConfigCtl.py
@@ -248,7 +248,7 @@ class PCStateConfigCtl(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_PKG_CST_CONFIG_CONTROL
     regname = "MSR_PKG_CST_CONFIG_CONTROL"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/PMEnable.py b/pepclibs/msr/PMEnable.py
@@ -51,7 +51,7 @@ class PMEnable(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_PM_ENABLE
     regname = "MSR_PM_ENABLE"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/PMLogicalId.py b/pepclibs/msr/PMLogicalId.py
@@ -76,7 +76,7 @@ class PMLogicalId(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_PM_LOGICAL_ID
     regname = "MSR_PM_LOGICAL_ID"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/PlatformInfo.py b/pepclibs/msr/PlatformInfo.py
@@ -115,7 +115,7 @@ class PlatformInfo(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_PLATFORM_INFO
     regname = "MSR_PLATFORM_INFO"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/PowerCtl.py b/pepclibs/msr/PowerCtl.py
@@ -115,7 +115,7 @@ class PowerCtl(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_POWER_CTL
     regname = "MSR_POWER_CTL"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/SwLTROvrd.py b/pepclibs/msr/SwLTROvrd.py
@@ -94,7 +94,7 @@ class SwLTROvrd(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_SW_LTR_OVRD
     regname = "MSR_SW_LTR_OVRD"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/TurboRatioLimit.py b/pepclibs/msr/TurboRatioLimit.py
@@ -106,7 +106,7 @@ class TurboRatioLimit(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_TURBO_RATIO_LIMIT
     regname = "MSR_TURBO_RATIO_LIMIT"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/TurboRatioLimit1.py b/pepclibs/msr/TurboRatioLimit1.py
@@ -56,7 +56,7 @@ class TurboRatioLimit1(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_TURBO_RATIO_LIMIT1
     regname = "MSR_TURBO_RATIO_LIMIT1"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
diff --git a/pepclibs/msr/UncoreRatioLimit.py b/pepclibs/msr/UncoreRatioLimit.py
@@ -79,7 +79,7 @@ class UncoreRatioLimit(_FeaturedMSR.FeaturedMSR):
 
     regaddr = MSR_UNCORE_RATIO_LIMIT
     regname = "MSR_UNCORE_RATIO_LIMIT"
-    vendor = "GenuineIntel"
+    vendor_name = "GenuineIntel"
 
     def __init__(self,
                  cpuinfo: CPUInfo.CPUInfo,
