[Codegen][AMDGPU] Add UseGlobalTransposeLoad promotion attr and operand promotion for RDNA4

[nirvedhmeshram]

Part of #24454. Stacks on #24457 and #24467.

Summary

Introduces IREEGPU_UseGlobalTransposeLoad, a promotion attribute that
drives matmul B-operands (and transposed A-operands) to be loaded via
global_load_tr on RDNA4 (gfx1200+).

New attribute

UseGlobalTransposeLoadAttr implements:

• IREEGPU_PromotionAttr — hooks into GPUPromoteMatmulOperands
• IREECodegen_LoweringConfigAttrInterface — provides tiling sizes [N=8, K=1]
  (vectorSize × 1, where vectorSize=8 for bf16/f16)

K-inner operand promotion

A new transposePromoteOperand path in GPUPromoteMatmulOperands creates
a linalg.generic copy with K-inner thread mapping:

• input map: (d0, d1) → (d1, d0) — reads B[K, N] (K-outer, N-inner in memory)
• output map: (d0, d1) → (d0, d1) — writes alloc[N, K] (N-outer, K-inner)

This tiling aligns with global_load_tr's 8×8 wave-level hardware transpose:
8 consecutive lanes each read 8 contiguous N-elements, and the hardware
transposes so each lane holds a K-direction slice. Consecutive lanes → K,
which is exactly what K-inner thread assignment gives.

The copy is tagged with UseGlobalTransposeLoadAttr as its lowering config
so ROCDLLoadToTransposeLoad (PR 2) can pattern-match and lower it.

amdgpu.fat_raw_buffer_cast is stripped before creating the copy because
global_load_tr requires a flat global pointer, not a fat buffer descriptor.

New helpers

• DerivedConfigUtils: globalTransposeLoadTileSizes(op) returns {vectorSize, 1}
• IREEGPUAttrs: UseGlobalTransposeLoadAttr tiling level implementation

Test

gpu_promote_matmul_operands_global_transpose.mlir verifies:

• RHS promotion: copy gets output shape [N, K] (transposed) with use_global_transpose_load config
• LHS promotion (transposedLhs): same attribute on the copy