Skip to content

Commit f4f6b8b

Browse files
panditsapanditsa
committed
pre-commit fixes
Signed-off-by: Sanket Pandit <sanket.pandit@amd.com> Made-with: Cursor
1 parent dd3b163 commit f4f6b8b

9 files changed

Lines changed: 63 additions & 66 deletions

File tree

‎waveasm/include/waveasm/Transforms/TranslateFromMLIR.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -377,8 +377,6 @@ class TranslationContext {
377377
/// Get next available SRD index
378378
int64_t getNextSRDIndex();
379379

380-
381-
382380
/// Update buffer size for a pending SRD (called when we see reinterpret_cast)
383381
void updateSRDBufferSize(mlir::Value memref, int64_t bufferSize);
384382

‎waveasm/lib/Transforms/AssemblyEmitter.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -358,8 +358,8 @@ KernelGenerator::emitScaledMFMA(Operation *scaledOp, llvm::StringRef mnemonic) {
358358
std::optional<std::string> KernelGenerator::generateOp(Operation *op) {
359359
return llvm::TypeSwitch<Operation *, std::optional<std::string>>(op)
360360
.Case<ProgramOp, LabelOp, CommentOp, PrecoloredVRegOp, PrecoloredSRegOp,
361-
PrecoloredARegOp, ConstantOp, PackOp, ExtractOp,
362-
DCEProtectOp>([](auto) { return std::nullopt; })
361+
PrecoloredARegOp, ConstantOp, PackOp, ExtractOp, DCEProtectOp>(
362+
[](auto) { return std::nullopt; })
363363
.Case<RawOp>([&](RawOp rawOp) -> std::optional<std::string> {
364364
return generateRaw(rawOp);
365365
})

‎waveasm/lib/Transforms/MetadataEmitter.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,6 +148,7 @@ static void scanSystemRegisterUsage(ProgramOp program, bool &usesWorkgroupIdX,
148148

149149
int64_t userSgprCount = 2;
150150
if (isGfx950) {
151+
// Hardware limits user SGPRs to 16 on gfx950.
151152
userSgprCount = std::min(int64_t(16), 2 + numArgs * 2);
152153
}
153154

@@ -205,15 +206,17 @@ MetadataEmitter::emitKernelDescriptor(int64_t peakVGPRs, int64_t peakSGPRs,
205206

206207
auto targetAttr = program.getTarget();
207208
auto targetKind = targetAttr.getTargetKind();
209+
int64_t preloadLength = program.getKernargPreloadLength();
208210
bool usePreloading = llvm::isa<GFX950TargetAttr>(targetKind);
209211

210-
int64_t preloadLength = program.getKernargPreloadLength();
211212
if (usePreloading && preloadLength == 0) {
212213
int64_t numArgs = 2;
213214
if (auto numArgsAttr =
214215
program->getAttrOfType<IntegerAttr>("num_kernel_args")) {
215216
numArgs = numArgsAttr.getInt();
216217
}
218+
// Hardware limits user SGPRs to 16 on gfx950 (2 for kernarg ptr + 14 max
219+
// preloaded). Overflow args are loaded via explicit s_load in the prologue.
217220
preloadLength = std::min(int64_t(14), numArgs * 2);
218221
}
219222

‎waveasm/lib/Transforms/TranslateFromMLIR.cpp‎

Lines changed: 9 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -250,8 +250,7 @@ void TranslationContext::emitSRDPrologue() {
250250
auto offsetImm = builder.getType<ImmType>(kernargOffset);
251251
auto offsetConst =
252252
ConstantOp::create(builder, loc, offsetImm, kernargOffset);
253-
auto loadOp = S_LOAD_DWORDX2::create(builder, loc,
254-
TypeRange{loadDstType},
253+
auto loadOp = S_LOAD_DWORDX2::create(builder, loc, TypeRange{loadDstType},
255254
kernargBase, offsetConst);
256255
argLoadResults[pending.argIndex] = loadOp->getResult(0);
257256
}
@@ -267,8 +266,7 @@ void TranslationContext::emitSRDPrologue() {
267266
auto offsetImm = builder.getType<ImmType>(kernargOffset);
268267
auto offsetConst =
269268
ConstantOp::create(builder, loc, offsetImm, kernargOffset);
270-
auto loadOp = S_LOAD_DWORDX2::create(builder, loc,
271-
TypeRange{loadDstType},
269+
auto loadOp = S_LOAD_DWORDX2::create(builder, loc, TypeRange{loadDstType},
272270
kernargBase, offsetConst);
273271
argLoadResults[pending.argIndex] = loadOp->getResult(0);
274272
}
@@ -305,8 +303,7 @@ void TranslationContext::emitSRDPrologue() {
305303
auto offsetImm = builder.getType<ImmType>(kernargOffset);
306304
auto offsetConst =
307305
ConstantOp::create(builder, loc, offsetImm, kernargOffset);
308-
auto loadOp = S_LOAD_DWORDX2::create(builder, loc,
309-
TypeRange{loadDstType},
306+
auto loadOp = S_LOAD_DWORDX2::create(builder, loc, TypeRange{loadDstType},
310307
kernargBase, offsetConst);
311308
overflowLoadResults[overflowIdx] = loadOp->getResult(0);
312309
overflowIdx++;
@@ -422,8 +419,7 @@ void TranslationContext::emitSRDPrologue() {
422419
auto offsetImm = builder.getType<ImmType>(kernargOffset);
423420
auto offsetConst =
424421
ConstantOp::create(builder, loc, offsetImm, kernargOffset);
425-
auto loadOp = S_LOAD_DWORDX2::create(builder, loc,
426-
TypeRange{loadDstType},
422+
auto loadOp = S_LOAD_DWORDX2::create(builder, loc, TypeRange{loadDstType},
427423
kernargBase, offsetConst);
428424
srdLoadResults[srdBase] = loadOp->getResult(0);
429425
}
@@ -437,8 +433,7 @@ void TranslationContext::emitSRDPrologue() {
437433
auto offsetImm = builder.getType<ImmType>(kernargOffset);
438434
auto offsetConst =
439435
ConstantOp::create(builder, loc, offsetImm, kernargOffset);
440-
auto loadOp = S_LOAD_DWORDX2::create(builder, loc,
441-
TypeRange{loadDstType},
436+
auto loadOp = S_LOAD_DWORDX2::create(builder, loc, TypeRange{loadDstType},
442437
kernargBase, offsetConst);
443438
scalarLoadResults[(int64_t)i] = loadOp->getResult(0);
444439
}
@@ -459,8 +454,8 @@ void TranslationContext::emitSRDPrologue() {
459454
auto loadIt = srdLoadResults.find(srdBase);
460455
if (loadIt != srdLoadResults.end()) {
461456
auto dstB64Type = PSRegType::get(builder.getContext(), srdBase, 2);
462-
auto movB64 = S_MOV_B64::create(builder, loc, dstB64Type,
463-
loadIt->second);
457+
auto movB64 =
458+
S_MOV_B64::create(builder, loc, dstB64Type, loadIt->second);
464459
DCEProtectOp::create(builder, loc, movB64);
465460
}
466461

@@ -495,8 +490,8 @@ void TranslationContext::emitSRDPrologue() {
495490
auto loadIt = scalarLoadResults.find((int64_t)i);
496491
if (loadIt != scalarLoadResults.end()) {
497492
auto sregTy = createSRegType(1, 1);
498-
Value lowWord = ExtractOp::create(builder, loc, sregTy,
499-
loadIt->second, 0);
493+
Value lowWord =
494+
ExtractOp::create(builder, loc, sregTy, loadIt->second, 0);
500495
auto dstPsType = PSRegType::get(builder.getContext(), sgprIdx, 1);
501496
auto movOp = S_MOV_B32::create(builder, loc, dstPsType, lowWord);
502497
DCEProtectOp::create(builder, loc, movOp);

‎waveasm/lib/Transforms/handlers/AMDGPUHandlers.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -435,16 +435,16 @@ static void patchSrdWord2InPlace(OpBuilder &builder, Location loc,
435435
isScalarOrImm(*cmpLhsMapped) && isScalarOrImm(*cmpRhsMapped) &&
436436
isScalarOrImm(*trueMapped) && isScalarOrImm(*falseMapped)) {
437437
Value sccVal = emitScalarCmp(builder, loc, cmpOp.getPredicate(),
438-
*cmpLhsMapped, *cmpRhsMapped, ctx);
438+
*cmpLhsMapped, *cmpRhsMapped, ctx);
439439

440440
auto dstType = PSRegType::get(builder.getContext(), srdBase + 2, 1);
441441
Value trueV = *trueMapped;
442442
Value falseV = *falseMapped;
443443
auto sregType = ctx.createSRegType();
444444
if (isImmType(trueV.getType()))
445445
trueV = S_MOV_B32::create(builder, loc, sregType, trueV);
446-
auto result =
447-
S_CSELECT_B32::create(builder, loc, dstType, sccVal, trueV, falseV);
446+
auto result = S_CSELECT_B32::create(builder, loc, dstType, sccVal,
447+
trueV, falseV);
448448
DCEProtectOp::create(builder, loc, result);
449449
return;
450450
}

‎waveasm/lib/Transforms/handlers/AffineHandlers.cpp‎

Lines changed: 16 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -422,7 +422,8 @@ static Value emitCeilFromFloorQuotient(Value q, Value x, Value d,
422422
// s_addc_u32: dst = q + 0 + SCC (carry-in from SCC)
423423
auto sregType = ctx.createSRegType();
424424
auto sccType = ctx.createSCCType();
425-
return S_ADDC_U32::create(builder, loc, sregType, sccType, sccVal, q, zeroConst)
425+
return S_ADDC_U32::create(builder, loc, sregType, sccType, sccVal, q,
426+
zeroConst)
426427
.getDst();
427428
}
428429
auto vregType = ctx.createVRegType();
@@ -629,12 +630,11 @@ LogicalResult handleAffineApply(Operation *op, TranslationContext &ctx) {
629630
auto shiftConst =
630631
ConstantOp::create(builder, loc, shiftImm, shiftAmount);
631632
// v_lshl_or_b32: dst = (src << shift) | orend
632-
Value base = ensureVGPR(builder, loc, ctx,
633-
baseResult.value);
633+
Value base =
634+
ensureVGPR(builder, loc, ctx, baseResult.value);
634635
orend = ensureVGPR(builder, loc, ctx, orend);
635636
Value fusedResult = V_LSHL_OR_B32::create(
636-
builder, loc, vregType, base, shiftConst,
637-
orend);
637+
builder, loc, vregType, base, shiftConst, orend);
638638
BitRange shiftedRange =
639639
baseResult.range.shiftLeft(shiftAmount);
640640
BitRange resultRange = shiftedRange.merge(orendRange);
@@ -652,12 +652,11 @@ LogicalResult handleAffineApply(Operation *op, TranslationContext &ctx) {
652652
auto shiftImm = ctx.createImmType(shiftAmount);
653653
auto shiftConst =
654654
ConstantOp::create(builder, loc, shiftImm, shiftAmount);
655-
Value base2 = ensureVGPR(builder, loc, ctx,
656-
baseResult.value);
655+
Value base2 =
656+
ensureVGPR(builder, loc, ctx, baseResult.value);
657657
orend = ensureVGPR(builder, loc, ctx, orend);
658658
Value fusedResult = V_LSHL_OR_B32::create(
659-
builder, loc, vregType, base2, shiftConst,
660-
orend);
659+
builder, loc, vregType, base2, shiftConst, orend);
661660
BitRange shiftedRange =
662661
baseResult.range.shiftLeft(shiftAmount);
663662
BitRange resultRange = shiftedRange.merge(orendRange);
@@ -751,8 +750,7 @@ LogicalResult handleAffineApply(Operation *op, TranslationContext &ctx) {
751750
auto shiftAmt = ctx.createImmType(shiftAmount);
752751
auto shiftConst =
753752
ConstantOp::create(builder, loc, shiftAmt, shiftAmount);
754-
Value shiftResult =
755-
emitLshl(lhs, shiftConst, builder, loc, ctx);
753+
Value shiftResult = emitLshl(lhs, shiftConst, builder, loc, ctx);
756754
BitRange resultRange = lhsRange.shiftLeft(shiftAmount);
757755
ctx.setBitRange(shiftResult, resultRange);
758756
return ExprResult(shiftResult, resultRange);
@@ -765,8 +763,7 @@ LogicalResult handleAffineApply(Operation *op, TranslationContext &ctx) {
765763
auto shiftAmt = ctx.createImmType(shiftAmount);
766764
auto shiftConst =
767765
ConstantOp::create(builder, loc, shiftAmt, shiftAmount);
768-
Value shiftResult =
769-
emitLshl(rhs, shiftConst, builder, loc, ctx);
766+
Value shiftResult = emitLshl(rhs, shiftConst, builder, loc, ctx);
770767
BitRange resultRange = rhsRange.shiftLeft(shiftAmount);
771768
ctx.setBitRange(shiftResult, resultRange);
772769
return ExprResult(shiftResult, resultRange);
@@ -799,8 +796,7 @@ LogicalResult handleAffineApply(Operation *op, TranslationContext &ctx) {
799796
auto shiftAmt = ctx.createImmType(shiftAmount);
800797
auto shiftConst =
801798
ConstantOp::create(builder, loc, shiftAmt, shiftAmount);
802-
Value shiftResult =
803-
emitLshr(lhs, shiftConst, builder, loc, ctx);
799+
Value shiftResult = emitLshr(lhs, shiftConst, builder, loc, ctx);
804800
BitRange resultRange = lhsRange.shiftRight(shiftAmount);
805801
ctx.setBitRange(shiftResult, resultRange);
806802
return ExprResult(shiftResult, resultRange);
@@ -835,14 +831,13 @@ LogicalResult handleAffineApply(Operation *op, TranslationContext &ctx) {
835831
Value rem = emitAnd(lhs, maskConst, builder, loc, ctx);
836832
Value zeroConst = createImmConst(0, builder, loc, ctx);
837833
if (isScalarOrImm(rem)) {
838-
Value sccVal = S_CMP_NE_U32::create(builder, loc,
839-
ctx.createSCCType(), rem, zeroConst);
834+
Value sccVal = S_CMP_NE_U32::create(
835+
builder, loc, ctx.createSCCType(), rem, zeroConst);
840836
auto sregType = ctx.createSRegType();
841837
auto sccType = ctx.createSCCType();
842-
Value result =
843-
S_ADDC_U32::create(builder, loc, sregType, sccType, sccVal, q,
844-
zeroConst)
845-
.getDst();
838+
Value result = S_ADDC_U32::create(builder, loc, sregType, sccType,
839+
sccVal, q, zeroConst)
840+
.getDst();
846841
return ExprResult(result, BitRange());
847842
}
848843
V_CMP_NE_U32::create(builder, loc, rem, zeroConst);

‎waveasm/lib/Transforms/handlers/ArithHandlers.cpp‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -537,23 +537,23 @@ LogicalResult handleArithSelect(Operation *op, TranslationContext &ctx) {
537537
if (auto cmpOp = condMLIR.getDefiningOp<arith::CmpIOp>()) {
538538
auto cmpLhs = ctx.getMapper().getMapped(cmpOp.getLhs());
539539
auto cmpRhs = ctx.getMapper().getMapped(cmpOp.getRhs());
540-
if (cmpLhs && cmpRhs &&
541-
isScalarOrImm(*cmpLhs) && isScalarOrImm(*cmpRhs)) {
540+
if (cmpLhs && cmpRhs && isScalarOrImm(*cmpLhs) &&
541+
isScalarOrImm(*cmpRhs)) {
542542
auto sregType = ctx.createSRegType();
543543
Value lhsOp = *cmpLhs;
544544
Value rhsOp = *cmpRhs;
545545
if (isImmType(lhsOp.getType()))
546546
lhsOp = S_MOV_B32::create(builder, loc, sregType, lhsOp);
547547
if (isImmType(rhsOp.getType()))
548548
rhsOp = S_MOV_B32::create(builder, loc, sregType, rhsOp);
549-
Value sccVal =
550-
emitScalarCmp(builder, loc, cmpOp.getPredicate(), lhsOp, rhsOp, ctx);
549+
Value sccVal = emitScalarCmp(builder, loc, cmpOp.getPredicate(), lhsOp,
550+
rhsOp, ctx);
551551
Value trueV = *trueVal;
552552
Value falseV = *falseVal;
553553
if (isImmType(trueV.getType()))
554554
trueV = S_MOV_B32::create(builder, loc, sregType, trueV);
555-
auto result =
556-
S_CSELECT_B32::create(builder, loc, sregType, sccVal, trueV, falseV);
555+
auto result = S_CSELECT_B32::create(builder, loc, sregType, sccVal,
556+
trueV, falseV);
557557
ctx.getMapper().mapValue(selectOp.getResult(), result);
558558
return success();
559559
}
@@ -568,14 +568,15 @@ LogicalResult handleArithSelect(Operation *op, TranslationContext &ctx) {
568568
Value condV = *cond;
569569
if (isImmType(condV.getType()))
570570
condV = S_MOV_B32::create(builder, loc, ctx.createSRegType(), condV);
571-
Value sccVal =
572-
S_CMP_NE_U32::create(builder, loc, ctx.createSCCType(), condV, zeroConst);
571+
Value sccVal = S_CMP_NE_U32::create(builder, loc, ctx.createSCCType(),
572+
condV, zeroConst);
573573
auto sregType = ctx.createSRegType();
574574
Value trueV = *trueVal;
575575
Value falseV = *falseVal;
576576
if (isImmType(trueV.getType()))
577577
trueV = S_MOV_B32::create(builder, loc, sregType, trueV);
578-
auto result = S_CSELECT_B32::create(builder, loc, sregType, sccVal, trueV, falseV);
578+
auto result =
579+
S_CSELECT_B32::create(builder, loc, sregType, sccVal, trueV, falseV);
579580
ctx.getMapper().mapValue(selectOp.getResult(), result);
580581
return success();
581582
}

‎waveasm/lib/Transforms/handlers/Handlers.h‎

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -308,8 +308,9 @@ inline mlir::Value ensureVGPR(mlir::OpBuilder &builder, mlir::Location loc,
308308

309309
/// Emit add: S_ADD_U32 when both operands are scalar, V_ADD_U32 otherwise.
310310
/// Commutative: swaps to put immediate in src1 (SALU src0 must be SGPR).
311-
inline mlir::Value emitAdd(mlir::Value a, mlir::Value b, mlir::OpBuilder &builder,
312-
mlir::Location loc, TranslationContext &ctx) {
311+
inline mlir::Value emitAdd(mlir::Value a, mlir::Value b,
312+
mlir::OpBuilder &builder, mlir::Location loc,
313+
TranslationContext &ctx) {
313314
if (isScalarOrImm(a) && isScalarOrImm(b) &&
314315
!(isImmType(a.getType()) && isImmType(b.getType()))) {
315316
if (isImmType(a.getType()))
@@ -324,8 +325,9 @@ inline mlir::Value emitAdd(mlir::Value a, mlir::Value b, mlir::OpBuilder &builde
324325

325326
/// Emit sub: S_SUB_U32 when both operands are scalar, V_SUB_U32 otherwise.
326327
/// Not commutative: src0 (minuend) must be SGPR.
327-
inline mlir::Value emitSub(mlir::Value a, mlir::Value b, mlir::OpBuilder &builder,
328-
mlir::Location loc, TranslationContext &ctx) {
328+
inline mlir::Value emitSub(mlir::Value a, mlir::Value b,
329+
mlir::OpBuilder &builder, mlir::Location loc,
330+
TranslationContext &ctx) {
329331
if (isScalarOrImm(a) && isScalarOrImm(b) && isSGPRType(a.getType())) {
330332
auto sregType = ctx.createSRegType();
331333
auto sccType = ctx.createSCCType();
@@ -337,8 +339,9 @@ inline mlir::Value emitSub(mlir::Value a, mlir::Value b, mlir::OpBuilder &builde
337339

338340
/// Emit mul: S_MUL_I32 when both operands are scalar, V_MUL_LO_U32 otherwise.
339341
/// Commutative: swaps to put immediate in src1.
340-
inline mlir::Value emitMul(mlir::Value a, mlir::Value b, mlir::OpBuilder &builder,
341-
mlir::Location loc, TranslationContext &ctx) {
342+
inline mlir::Value emitMul(mlir::Value a, mlir::Value b,
343+
mlir::OpBuilder &builder, mlir::Location loc,
344+
TranslationContext &ctx) {
342345
if (isScalarOrImm(a) && isScalarOrImm(b) &&
343346
!(isImmType(a.getType()) && isImmType(b.getType()))) {
344347
if (isImmType(a.getType()))
@@ -386,8 +389,9 @@ inline mlir::Value emitLshl(mlir::Value value, mlir::Value shiftAmt,
386389

387390
/// Emit bitwise AND: S_AND_B32 when both scalar, V_AND_B32 otherwise.
388391
/// Commutative: swaps to put immediate in src1.
389-
inline mlir::Value emitAnd(mlir::Value a, mlir::Value b, mlir::OpBuilder &builder,
390-
mlir::Location loc, TranslationContext &ctx) {
392+
inline mlir::Value emitAnd(mlir::Value a, mlir::Value b,
393+
mlir::OpBuilder &builder, mlir::Location loc,
394+
TranslationContext &ctx) {
391395
if (isScalarOrImm(a) && isScalarOrImm(b) &&
392396
!(isImmType(a.getType()) && isImmType(b.getType()))) {
393397
if (isImmType(a.getType()))
@@ -402,8 +406,9 @@ inline mlir::Value emitAnd(mlir::Value a, mlir::Value b, mlir::OpBuilder &builde
402406

403407
/// Emit bitwise OR: S_OR_B32 when both scalar, V_OR_B32 otherwise.
404408
/// Commutative: swaps to put immediate in src1.
405-
inline mlir::Value emitOr(mlir::Value a, mlir::Value b, mlir::OpBuilder &builder,
406-
mlir::Location loc, TranslationContext &ctx) {
409+
inline mlir::Value emitOr(mlir::Value a, mlir::Value b,
410+
mlir::OpBuilder &builder, mlir::Location loc,
411+
TranslationContext &ctx) {
407412
if (isScalarOrImm(a) && isScalarOrImm(b) &&
408413
!(isImmType(a.getType()) && isImmType(b.getType()))) {
409414
if (isImmType(a.getType()))
@@ -418,8 +423,9 @@ inline mlir::Value emitOr(mlir::Value a, mlir::Value b, mlir::OpBuilder &builder
418423

419424
/// Emit bitwise XOR: S_XOR_B32 when both scalar, V_XOR_B32 otherwise.
420425
/// Commutative: swaps to put immediate in src1.
421-
inline mlir::Value emitXor(mlir::Value a, mlir::Value b, mlir::OpBuilder &builder,
422-
mlir::Location loc, TranslationContext &ctx) {
426+
inline mlir::Value emitXor(mlir::Value a, mlir::Value b,
427+
mlir::OpBuilder &builder, mlir::Location loc,
428+
TranslationContext &ctx) {
423429
if (isScalarOrImm(a) && isScalarOrImm(b) &&
424430
!(isImmType(a.getType()) && isImmType(b.getType()))) {
425431
if (isImmType(a.getType()))

‎waveasm/lib/Transforms/handlers/MemRefHandlers.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -305,8 +305,7 @@ LogicalResult handleMemRefStore(Operation *op, TranslationContext &ctx) {
305305
Value storeData = *data;
306306
if (isAGPRType(storeData.getType())) {
307307
auto vregType = ctx.createVRegType();
308-
storeData =
309-
V_ACCVGPR_READ_B32::create(builder, loc, vregType, storeData);
308+
storeData = V_ACCVGPR_READ_B32::create(builder, loc, vregType, storeData);
310309
}
311310

312311
BUFFER_STORE_DWORD::create(builder, loc, storeData, srd, voffset,

0 commit comments

Comments
 (0)