-
Notifications
You must be signed in to change notification settings - Fork 1
Expand file tree
/
Copy pathstateMachineLVS.net
More file actions
145 lines (137 loc) · 5.09 KB
/
stateMachineLVS.net
File metadata and controls
145 lines (137 loc) · 5.09 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
* Z:\home\sbecht\ultra-efficient-adc\stateMachineLVS.asc
XX1 CO CLK N015 N014 Vdd 0 spdtlvs
XX2 N015 N016 Vdd 0 inverter
XX3 N016 N010 Vdd 0 inverter
XX4 N001 N010 N016 N005 N017 RST Vdd 0 resetflipflop_high_lds
XX5 N005 N010 N016 N006 N019 RSTb Vdd 0 resetflipflop_low_lds
XX6 N006 N010 N016 Q N012 RSTb Vdd 0 resetflipflop_low_lds
XX7 N003 N007 N012 Vdd 0 nandlvs
XX8 N007 N010 N016 N008 N020 RSTb Vdd 0 resetflipflop_low_lds
XX9 N008 N010 N016 N009 N018 RSTb Vdd 0 resetflipflop_low_lds
XX10 N009 N010 N016 N002 N013 RSTb Vdd 0 resetflipflop_low_lds
XX11 N002 N003 GO? Vdd 0 nandlvs
XX12 GO? N004 N013 Vdd 0 norlvs
XX13 N004 N010 N016 N001 N011 RSTb Vdd 0 resetflipflop_low_lds
XX15 N011 N021 Vdd 0 inverter
XX14 N021 N024 Vdd 0 inverter
XX16 N024 N025 Vdd 0 inverter
XX17 N025 N028 Vdd 0 inverter
XX18 N028 W_OUT Vdd 0 inverter
XX19 N012 N018 N013 Vdd 0 N014 nand3lvs
XX20 N017 RST_IR Vdd 0 inverter
XX21 N019 N022 N017 Vdd 0 nandlvs
XX22 N011 N023 N020 Vdd 0 nandlvs
XX23 N023 N027 N022 Vdd 0 norlvs
XX24 N027 DIS_CO? Vdd 0 inverter
XX25 N019 Iin? Vdd 0 inverter
XX26 N012 MSB_CE Vdd 0 inverter
XX27 N020 N013 N019 Vdd 0 C1? nand3lvs
XX28 N018 C2? N012 Vdd 0 nandlvs
XX29 N013 RST_C2_CO? N012 Vdd 0 nandlvs
XX30 RST_C2_CO? N026 Vdd 0 inverter
XX31 N018 RST_C1_CO? N026 Vdd 0 nandlvs
XX32 N013 LSB_CE N018 Vdd 0 nandlvs
XX33 N013 C2Ref? Vdd 0 inverter
* block symbol definitions
.subckt spdtlvs IN1 IN2 OUT S V+ V-
M1 V+ S N001 V+ pfet l=.9u w=6u
M2 V- S N001 V- nfet l=.9u w=3u
M3 IN1 S OUT V- nfet l=.9u w=3u
M4 IN2 S OUT V+ pfet l=.9u w=6u
M5 OUT N001 IN2 V- nfet l=.9u w=3u
M6 OUT N001 IN1 V+ pfet l=.9u w=6u
.ends spdtlvs
.subckt inverter IN OUT pos neg
M1 OUT IN neg neg nfet l=.9u w=3u
M2 OUT IN pos pos pfet l=.9u w=6u
.ends inverter
.subckt resetflipflop_high_lds D CLK CLKb Q Qb RESET pos neg
M1 N007 D neg neg nfet l=0.9u w=3u
M2 N003 D pos pos pfet l=0.9u w=6u
M3 N001 RESET neg neg nfet l=0.9u w=4.5u
M4 N005 CLKb N003 pos pfet l=0.9u w=6u
M5 N002 N005 pos pos pfet l=0.9u w=6u
M6 N001 CLK N004 pos pfet l=0.9u w=6u
M7 N004 N002 pos pos pfet l=0.9u w=6u
M8 Q N001 pos pos pfet l=0.9u w=6u
M9 N006 N001 pos pos pfet l=0.9u w=6u
M10 pos N002 N010 pos pfet l=0.9u w=6u
M11 N010 CLK N005 pos pfet l=0.9u w=6u
M12 N009 CLKb N001 pos pfet l=0.9u w=6u
M13 pos N006 N009 pos pfet l=0.9u w=6u
M14 Qb N006 pos pos pfet l=0.9u w=6u
M15 N005 CLK N007 neg nfet l=0.9u w=3u
M16 N002 N005 neg neg nfet l=0.9u w=3u
M17 N001 CLKb N008 neg nfet l=0.9u w=3u
M18 N008 N002 neg neg nfet l=0.9u w=3u
M19 N006 N001 neg neg nfet l=0.9u w=3u
M20 Qb N006 neg neg nfet l=0.9u w=3u
M21 N001 CLK N011 neg nfet l=0.9u w=3u
M22 N011 N006 neg neg nfet l=0.9u w=3u
M23 N005 CLKb N012 neg nfet l=0.9u w=3u
M24 N012 N002 neg neg nfet l=0.9u w=3u
M25 N001 RESET neg neg nfet l=0.9u w=4.5u
M26 N001 RESET neg neg nfet l=0.9u w=4.5u
M27 N001 RESET neg neg nfet l=0.9u w=4.5u
M28 N005 RESET neg neg nfet l=0.9u w=4.5u
M29 N005 RESET neg neg nfet l=0.9u w=4.5u
M30 N005 RESET neg neg nfet l=0.9u w=4.5u
M31 N005 RESET neg neg nfet l=0.9u w=4.5u
M32 Q N001 neg neg nfet l=0.9u w=3u
.ends resetflipflop_high_lds
.subckt resetflipflop_low_lds D CLK CLKb Q Qb RESETb pos neg
M1 N005 CLK N007 neg nfet l=0.9u w=3u
M4 N003 D pos pos pfet l=0.9u w=6u
M28 N001 RESETb pos pos pfet l=0.9u w=7.8u
M29 N001 RESETb pos pos pfet l=0.9u w=12.6u
M3 N005 CLKb N003 pos pfet l=0.9u w=6u
M6 N002 N005 pos pos pfet l=0.9u w=6u
M9 N001 CLK N004 pos pfet l=0.9u w=6u
M10 N004 N002 pos pos pfet l=0.9u w=6u
M11 N006 N001 pos pos pfet l=0.9u w=6u
M12 Q N001 pos pos pfet l=0.9u w=6u
M16 Qb N006 pos pos pfet l=0.9u w=6u
M17 N001 CLKb N009 pos pfet l=0.9u w=6u
M18 N009 N006 pos pos pfet l=0.9u w=6u
M22 N005 CLK N010 pos pfet l=0.9u w=6u
M24 N010 N002 pos pos pfet l=0.9u w=6u
M2 N007 D neg neg nfet l=0.9u w=3u
M5 N002 N005 neg neg nfet l=0.9u w=3u
M7 N001 CLKb N008 neg nfet l=0.9u w=3u
M8 N008 N002 neg neg nfet l=0.9u w=3u
M13 N006 N001 neg neg nfet l=0.9u w=3u
M14 Qb N006 neg neg nfet l=0.9u w=3u
M15 N001 CLK N011 neg nfet l=0.9u w=3u
M19 N011 N006 neg neg nfet l=0.9u w=3u
M20 N012 N002 neg neg nfet l=0.9u w=3u
M21 N005 CLKb N012 neg nfet l=0.9u w=3u
M25 N001 RESETb pos pos pfet l=0.9u w=7.8u
M26 N001 RESETb pos pos pfet l=0.9u w=7.8u
M27 N005 RESETb pos pos pfet l=0.9u w=7.8u
M30 N005 RESETb pos pos pfet l=0.9u w=12.6u
M31 N005 RESETb pos pos pfet l=0.9u w=7.8u
M32 N005 RESETb pos pos pfet l=0.9u w=7.8u
M23 Q N001 neg neg nfet l=0.9u w=3u
.ends resetflipflop_low_lds
.subckt nandlvs A OUT B pos neg
M1 pos A OUT pos pfet l=.9u w=6u
M2 OUT B pos pos pfet l=.9u w=6u
M3 N001 A neg neg nfet l=.9u w=3u
M4 OUT B N001 neg nfet l=.9u w=3u
.ends nandlvs
.subckt norlvs A Out B Vdd neg
M1 Out B neg neg nfet l=.9u w=3u
M2 neg A Out neg nfet l=.9u w=3u
M3 Vdd B N001 Vdd pfet l=.9u w=6u
M4 N001 A Out Vdd pfet l=.9u w=6u
.ends norlvs
.subckt nand3lvs A B C pos neg OUT
M1 pos A OUT pos pfet l=.9u w=6u
M2 OUT B pos pos pfet l=.9u w=6u
M3 pos C OUT pos pfet l=.9u w=6u
M4 N001 A neg neg nfet l=.9u w=3u
M5 N002 B N001 neg nfet l=.9u w=3u
M6 OUT C N002 neg nfet l=.9u w=3u
.ends nand3lvs
.backanno
.end