|
| 1 | +/* |
| 2 | + * This file is part of the MicroPython project, http://micropython.org/ |
| 3 | + * |
| 4 | + * The MIT License (MIT) |
| 5 | + * |
| 6 | + * Copyright (c) 2021 Jim Mussared |
| 7 | + * |
| 8 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 9 | + * of this software and associated documentation files (the "Software"), to deal |
| 10 | + * in the Software without restriction, including without limitation the rights |
| 11 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 12 | + * copies of the Software, and to permit persons to whom the Software is |
| 13 | + * furnished to do so, subject to the following conditions: |
| 14 | + * |
| 15 | + * The above copyright notice and this permission notice shall be included in |
| 16 | + * all copies or substantial portions of the Software. |
| 17 | + * |
| 18 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 21 | + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 24 | + * THE SOFTWARE. |
| 25 | + */ |
| 26 | + |
| 27 | +// This is a translation of the cycle counter implementation in ports/stm32/machine_bitstream.c. |
| 28 | +// part of the code from robert-h w600 micropython port |
| 29 | + |
| 30 | +#include "py/mpconfig.h" |
| 31 | +#include "py/mphal.h" |
| 32 | + |
| 33 | +#if MICROPY_PY_MACHINE_BITSTREAM |
| 34 | + |
| 35 | +#define mp_hal_quiet_timing_enter() MICROPY_BEGIN_ATOMIC_SECTION() |
| 36 | +#define mp_hal_quiet_timing_exit(irq_state) MICROPY_END_ATOMIC_SECTION(irq_state) |
| 37 | + |
| 38 | +// NRF52840 @ 64MHz (cycle=15.625ns) |
| 39 | +#define NS_CYCLES_PER_ITER_HIGH (4) // 6 => 4 |
| 40 | +#define NS_CYCLES_PER_ITER_LOW (4) // 6 => 4 |
| 41 | +#define NS_OVERHEAD_CYCLES_HIGH (16) // 12 => 16 |
| 42 | +#define NS_OVERHEAD_CYCLES_LOW (12) // 18 => 12 |
| 43 | + |
| 44 | +uint32_t mp_hal_delay_ns_calc(uint32_t ns, bool high) { |
| 45 | + uint32_t ncycles = 64 * ns / 1000; // hard coded system clock 64MHz for NRF52. the system clock cannot be change anyway |
| 46 | + uint32_t overhead = MIN(ncycles, high ? NS_OVERHEAD_CYCLES_HIGH : NS_OVERHEAD_CYCLES_LOW); |
| 47 | + return MAX(1, MP_ROUND_DIVIDE(ncycles - overhead, high ? NS_CYCLES_PER_ITER_HIGH : NS_CYCLES_PER_ITER_LOW)); |
| 48 | +} |
| 49 | + |
| 50 | +void machine_bitstream_high_low(mp_hal_pin_obj_t p, uint32_t *timing_ns, const uint8_t *buf, size_t len) { |
| 51 | + uint32_t pin = p->pin; |
| 52 | + uint32_t reg; |
| 53 | + if (pin >= 32) { |
| 54 | + pin -= 32; |
| 55 | + reg = NRF_P1_BASE + 0x504; |
| 56 | + NRF_P1->DIRSET = (1 << pin); |
| 57 | + } else { |
| 58 | + reg = NRF_P0_BASE + 0x504; |
| 59 | + NRF_P0->DIRSET = (1 << pin); |
| 60 | + } |
| 61 | + uint32_t lo_mask = ~(1 << pin); |
| 62 | + uint32_t hi_mask = 1 << pin; |
| 63 | + |
| 64 | + // Convert ns to loop iterations [high_time_0, low_time_0, high_time_1, low_time_1]. |
| 65 | + |
| 66 | + for (size_t i = 0; i < 4; ++i) { |
| 67 | + timing_ns[i] = mp_hal_delay_ns_calc(timing_ns[i], i % 2 == 0); |
| 68 | + } |
| 69 | + |
| 70 | + uint32_t irq_state = mp_hal_quiet_timing_enter(); |
| 71 | + |
| 72 | + __asm volatile ( |
| 73 | + // Force consistent register assignment. |
| 74 | + // r6 = len |
| 75 | + "ldr r6, %0\n" |
| 76 | + // r4 = buf |
| 77 | + "ldr r4, %1\n" |
| 78 | + // r5 = timing_ms |
| 79 | + "ldr r5, %2\n" |
| 80 | + // r1 = GPIO reg |
| 81 | + "ldr r1, %5\n" |
| 82 | + // r8 GPIO reg value |
| 83 | + "ldr r8, [r1, #0]\n" |
| 84 | + // r9 Hi-Mask |
| 85 | + "ldr r9, %3\n" |
| 86 | + // r10 Lo-Mask |
| 87 | + "ldr r10, %4\n" |
| 88 | + |
| 89 | + // // Must align for consistent timing. |
| 90 | + ".align 4\n" |
| 91 | + |
| 92 | + // Don't increment/decrement before first iteration. |
| 93 | + "b .outer2\n" |
| 94 | + ".outer:\n" |
| 95 | + // ++buf, --len |
| 96 | + " add r4, #1\n" |
| 97 | + " sub r6, #1\n" |
| 98 | + |
| 99 | + // len iterations |
| 100 | + ".outer2:\n" |
| 101 | + " cmp r6, #0\n" |
| 102 | + " beq .done\n" |
| 103 | + // r0 = *buf |
| 104 | + " ldrb r0, [r4, #0]\n" |
| 105 | + |
| 106 | + // 8 bits in byte |
| 107 | + " mov r7, #8\n" |
| 108 | + // Reload the port value at every byte |
| 109 | + " ldr r8, [r1, #0]\n" |
| 110 | + " .inner:\n" |
| 111 | + // *(TLS_REG *)reg |= hi_mask; |
| 112 | + " orr r8, r9\n" |
| 113 | + " str r8, [r1, #0]\n" |
| 114 | + |
| 115 | + // r3 = (r0 >> 4) & 8 (r0 is 8 if high bit is 1 else 0) |
| 116 | + " mov r2, r6\n" |
| 117 | + " lsr r3, r0, #4\n" |
| 118 | + " mov r6, #8\n" |
| 119 | + " and r3, r6\n" |
| 120 | + " mov r6, r2\n" |
| 121 | + |
| 122 | + // r2 = timing_ns[r3] |
| 123 | + " ldr r2, [r5, r3]\n" |
| 124 | + " .loop1:\n sub r2, #1\n cmp r2, #0\n bne .loop1\n" |
| 125 | + |
| 126 | + // *(TLS_REG *)reg &= lo_mask; |
| 127 | + " and r8, r10\n" |
| 128 | + " str r8, [r1, #0]\n" |
| 129 | + |
| 130 | + // r2 = timing_ns[r3 + 4] |
| 131 | + " add r3, #4\n" |
| 132 | + " ldr r2, [r5, r3]\n" |
| 133 | + " .loop2:\n sub r2, #1\n cmp r2, #0\n bne .loop2\n" |
| 134 | + |
| 135 | + // b >>= 1 |
| 136 | + " lsl r0, r0, #1\n" |
| 137 | + " sub r7, #1\n" |
| 138 | + // continue inner loop |
| 139 | + " cmp r7, #0\n" |
| 140 | + " bne .inner\n" |
| 141 | + // continue outer loop |
| 142 | + " b .outer\n" |
| 143 | + |
| 144 | + ".done:\n" |
| 145 | + : |
| 146 | + : "m" (len), "m" (buf), "m" (timing_ns), "m" (hi_mask), "m" (lo_mask), "m" (reg) |
| 147 | + : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" |
| 148 | + ); |
| 149 | + |
| 150 | + mp_hal_quiet_timing_exit(irq_state); |
| 151 | + |
| 152 | +} |
| 153 | + |
| 154 | + |
| 155 | +#endif // MICROPY_PY_MACHINE_BITSTREAM |
0 commit comments