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[pre-commit.ci] pre-commit autoupdate #46

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095b5a9
[pre-commit.ci] pre-commit autoupdate
pre-commit-ci[bot] Jun 29, 2026
e7a129e
[pre-commit.ci] auto fixes from pre-commit.com hooks
pre-commit-ci[bot] Jun 29, 2026
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8 changes: 4 additions & 4 deletions .pre-commit-config.yaml
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
exclude: ^(src/plat/imx8x/sci|include/plat/imx8x/sci)
repos:
- repo: https://github.com/pre-commit/pre-commit-hooks
rev: v4.5.0
rev: v6.0.0
hooks:
- id: check-added-large-files
- id: check-case-conflict
Expand All @@ -15,7 +15,7 @@ repos:
- id: trailing-whitespace

- repo: https://github.com/pre-commit/mirrors-mypy
rev: v1.8.0
rev: v2.1.0
hooks:
- id: mypy
additional_dependencies:
Expand All @@ -26,12 +26,12 @@ repos:
args: ["."]

- repo: https://github.com/astral-sh/ruff-pre-commit
rev: v0.2.1
rev: v0.15.20
hooks:
- id: ruff
args: [ --fix ]

- repo: https://github.com/pre-commit/mirrors-clang-format
rev: v17.0.6
rev: v22.1.5
hooks:
- id: clang-format
116 changes: 58 additions & 58 deletions include/drivers/mmc/mmc_core.h
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Expand Up @@ -148,73 +148,73 @@

#define MMC_RSP_NONE (0)
#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)

/* Value randomly chosen for eMMC RCA, it should be > 1 */
#define MMC_FIX_RCA 10
#define RCA_SHIFT_OFFSET 16
#define MMC_FIX_RCA 10
#define RCA_SHIFT_OFFSET 16

/*
* Flags
*/

#define OCR_POWERUP BIT(31)
#define OCR_HCS BIT(30)
#define OCR_BYTE_MODE (0 << 29)
#define OCR_SECTOR_MODE (2 << 29)
#define OCR_ACCESS_MODE_MASK (3 << 29)
#define OCR_3_5_3_6 BIT(23)
#define OCR_3_4_3_5 BIT(22)
#define OCR_3_3_3_4 BIT(21)
#define OCR_3_2_3_3 BIT(20)
#define OCR_3_1_3_2 BIT(19)
#define OCR_3_0_3_1 BIT(18)
#define OCR_2_9_3_0 BIT(17)
#define OCR_2_8_2_9 BIT(16)
#define OCR_2_7_2_8 BIT(15)
#define OCR_VDD_MIN_2V7 GENMASK(23, 15)
#define OCR_VDD_MIN_2V0 GENMASK(14, 8)
#define OCR_VDD_MIN_1V7 BIT(7)

#define MMC_GET_STATE(x) (((x) >> 9) & 0xf)
#define MMC_STATE_IDLE 0
#define MMC_STATE_READY 1
#define MMC_STATE_IDENT 2
#define MMC_STATE_STBY 3
#define MMC_STATE_TRAN 4
#define MMC_STATE_DATA 5
#define MMC_STATE_RCV 6
#define MMC_STATE_PRG 7
#define MMC_STATE_DIS 8
#define MMC_STATE_BTST 9
#define MMC_STATE_SLP 10

#define STATUS_READY_FOR_DATA BIT(8)
#define STATUS_SWITCH_ERROR BIT(7)

#define EXTCSD_SET_CMD (U(0) << 24)
#define EXTCSD_SET_BITS (U(1) << 24)
#define EXTCSD_CLR_BITS (U(2) << 24)
#define EXTCSD_WRITE_BYTES (U(3) << 24)
#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
#define EXTCSD_CMD_SET_NORMAL U(1)

#define MMC_BLOCK_SIZE U(512)
#define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1))
#define MMC_BOOT_CLK_RATE (400 * 1000)
#define OCR_POWERUP BIT(31)
#define OCR_HCS BIT(30)
#define OCR_BYTE_MODE (0 << 29)
#define OCR_SECTOR_MODE (2 << 29)
#define OCR_ACCESS_MODE_MASK (3 << 29)
#define OCR_3_5_3_6 BIT(23)
#define OCR_3_4_3_5 BIT(22)
#define OCR_3_3_3_4 BIT(21)
#define OCR_3_2_3_3 BIT(20)
#define OCR_3_1_3_2 BIT(19)
#define OCR_3_0_3_1 BIT(18)
#define OCR_2_9_3_0 BIT(17)
#define OCR_2_8_2_9 BIT(16)
#define OCR_2_7_2_8 BIT(15)
#define OCR_VDD_MIN_2V7 GENMASK(23, 15)
#define OCR_VDD_MIN_2V0 GENMASK(14, 8)
#define OCR_VDD_MIN_1V7 BIT(7)

#define MMC_GET_STATE(x) (((x) >> 9) & 0xf)
#define MMC_STATE_IDLE 0
#define MMC_STATE_READY 1
#define MMC_STATE_IDENT 2
#define MMC_STATE_STBY 3
#define MMC_STATE_TRAN 4
#define MMC_STATE_DATA 5
#define MMC_STATE_RCV 6
#define MMC_STATE_PRG 7
#define MMC_STATE_DIS 8
#define MMC_STATE_BTST 9
#define MMC_STATE_SLP 10

#define STATUS_READY_FOR_DATA BIT(8)
#define STATUS_SWITCH_ERROR BIT(7)

#define EXTCSD_SET_CMD (U(0) << 24)
#define EXTCSD_SET_BITS (U(1) << 24)
#define EXTCSD_CLR_BITS (U(2) << 24)
#define EXTCSD_WRITE_BYTES (U(3) << 24)
#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
#define EXTCSD_CMD_SET_NORMAL U(1)

#define MMC_BLOCK_SIZE U(512)
#define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1))
#define MMC_BOOT_CLK_RATE (400 * 1000)

/* EXT_CSD_BOOT_BUS_CONDITIONS */
#define EXT_CSD_BOOT_SDR_HS BIT(3)
#define EXT_CSD_BOOT_DDR BIT(4)
#define EXT_CSD_BOOT_BUS_WIDTH_4 BIT(0)
#define EXT_CSD_BOOT_BUS_WIDTH_8 BIT(1)
#define EXT_CSD_BOOT_SDR_HS BIT(3)
#define EXT_CSD_BOOT_DDR BIT(4)
#define EXT_CSD_BOOT_BUS_WIDTH_4 BIT(0)
#define EXT_CSD_BOOT_BUS_WIDTH_8 BIT(1)

enum mmc_part {
MMC_PART_USER = 0,
Expand Down
8 changes: 4 additions & 4 deletions include/pb/utils_def.h
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Expand Up @@ -18,7 +18,7 @@
/* Compute the number of elements in the given array */
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))

#define IS_POWER_OF_TWO(x) (((x) & ((x)-1)) == 0)
#define IS_POWER_OF_TWO(x) (((x) & ((x) - 1)) == 0)

#define SIZE_FROM_LOG2_WORDS(n) (4 << (n))

Expand Down Expand Up @@ -56,7 +56,7 @@
* This variant of div_round_up can be used in macro definition but should not
* be used in C code as the `div` parameter is evaluated twice.
*/
#define DIV_ROUND_UP_2EVAL(n, d) (((n) + (d)-1) / (d))
#define DIV_ROUND_UP_2EVAL(n, d) (((n) + (d) - 1) / (d))

#define div_round_up(val, div) \
__extension__({ \
Expand Down Expand Up @@ -88,9 +88,9 @@
*
* round_down() is similar but rounds the value down instead.
*/
#define round_boundary(value, boundary) ((__typeof__(value))((boundary)-1))
#define round_boundary(value, boundary) ((__typeof__(value))((boundary) - 1))

#define round_up(value, boundary) ((((value)-1) | round_boundary(value, boundary)) + 1)
#define round_up(value, boundary) ((((value) - 1) | round_boundary(value, boundary)) + 1)

#define round_down(value, boundary) ((value) & ~round_boundary(value, boundary))

Expand Down
6 changes: 3 additions & 3 deletions include/plat/imx6ul/clock.h
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Expand Up @@ -19,9 +19,9 @@
#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK (0x3 << CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT)
#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL(x) \
((x << CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT) & CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK)
#define CCM_CSCMR1_QSPI1_PODF_SHIFT (26)
#define CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << CCM_CSCMR1_QSPI1_PODF_SHIFT)
#define CCM_CSCMR1_QSPI1_PODF(x) ((x << CCM_CSCMR1_QSPI1_PODF_SHIFT) & CCM_CSCMR1_QSPI1_PODF_MASK)
#define CCM_CSCMR1_QSPI1_PODF_SHIFT (26)
#define CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << CCM_CSCMR1_QSPI1_PODF_SHIFT)
#define CCM_CSCMR1_QSPI1_PODF(x) ((x << CCM_CSCMR1_QSPI1_PODF_SHIFT) & CCM_CSCMR1_QSPI1_PODF_MASK)
#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT (23)
#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK (0x7 << CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT)
#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF(x) \
Expand Down
54 changes: 27 additions & 27 deletions include/plat/imx6ul/mm.h
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Expand Up @@ -15,40 +15,40 @@
#define IMX6UL_SRC_SCR (0x020D8000)
#define SRC_SCR_MASK_WDOG_RST_SHIFT (7)
#define SRC_SCR_MASK_WDOG_RST_MASK (0xf << SRC_SCR_MASK_WDOG_RST_SHIFT)
#define SRC_SCR_MASK_WDOG_RST(x) ((x << SRC_SCR_MASK_WDOG_RST_SHIFT) & SRC_SCR_MASK_WDOG_RST_MASK)
#define SRC_SCR_WARM_RESET_ENABLE BIT(0)
#define SRC_SCR_MASK_WDOG_RST(x) ((x << SRC_SCR_MASK_WDOG_RST_SHIFT) & SRC_SCR_MASK_WDOG_RST_MASK)
#define SRC_SCR_WARM_RESET_ENABLE BIT(0)

#define IMX6UL_WDOG1_BASE (0x020BC000)
#define IMX6UL_GPT1_BASE (0x02098000)
#define IMX6UL_WDOG1_BASE (0x020BC000)
#define IMX6UL_GPT1_BASE (0x02098000)

#define IMX6UL_SRC_SRSR (0x020D8008)
#define IMX6UL_OCOTP_CTRL_BASE (0x021BC000)
#define IMX6UL_SRC_SRSR (0x020D8008)
#define IMX6UL_OCOTP_CTRL_BASE (0x021BC000)

#define IMX6UL_UART8_BASE (0x02024000)
#define IMX6UL_UART7_BASE (0x02018000)
#define IMX6UL_UART6_BASE (0x021FC000)
#define IMX6UL_UART5_BASE (0x021F4000)
#define IMX6UL_UART4_BASE (0x021F0000)
#define IMX6UL_UART3_BASE (0x021EC000)
#define IMX6UL_UART2_BASE (0x021E8000)
#define IMX6UL_UART1_BASE (0x02020000)
#define IMX6UL_UART8_BASE (0x02024000)
#define IMX6UL_UART7_BASE (0x02018000)
#define IMX6UL_UART6_BASE (0x021FC000)
#define IMX6UL_UART5_BASE (0x021F4000)
#define IMX6UL_UART4_BASE (0x021F0000)
#define IMX6UL_UART3_BASE (0x021EC000)
#define IMX6UL_UART2_BASE (0x021E8000)
#define IMX6UL_UART1_BASE (0x02020000)

#define IMX6UL_USDHC2_BASE (0x02194000)
#define IMX6UL_USDHC1_BASE (0x02190000)
#define IMX6UL_USDHC2_BASE (0x02194000)
#define IMX6UL_USDHC1_BASE (0x02190000)

#define IMX6UL_GPIO5_BASE (0x020AC000)
#define IMX6UL_GPIO4_BASE (0x020A8000)
#define IMX6UL_GPIO3_BASE (0x020A4000)
#define IMX6UL_GPIO2_BASE (0x020A0000)
#define IMX6UL_GPIO1_BASE (0x0209C000)
#define IMX6UL_GPIO5_BASE (0x020AC000)
#define IMX6UL_GPIO4_BASE (0x020A8000)
#define IMX6UL_GPIO3_BASE (0x020A4000)
#define IMX6UL_GPIO2_BASE (0x020A0000)
#define IMX6UL_GPIO1_BASE (0x0209C000)

#define IMX6UL_CAAM_BASE (0x02140000)
#define IMX6UL_CAAM_JR1_BASE (0x02141000)
#define IMX6UL_CAAM_BASE (0x02140000)
#define IMX6UL_CAAM_JR1_BASE (0x02141000)

#define IMX6UL_USBPHY1_BASE (0x020C9000)
#define IMX6UL_USBPHY2_BASE (0x020CA000)
#define IMX6UL_USBPHY1_BASE (0x020C9000)
#define IMX6UL_USBPHY2_BASE (0x020CA000)

#define IMX6UL_USB1_BASE (0x02184000)
#define IMX6UL_USB2_BASE (0x02184200)
#define IMX6UL_USB1_BASE (0x02184000)
#define IMX6UL_USB2_BASE (0x02184200)

#endif
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