2626#ifndef OS_CPU_LINUX_AARCH64_ICACHE_AARCH64_HPP
2727#define OS_CPU_LINUX_AARCH64_ICACHE_AARCH64_HPP
2828
29- #include " memory/allocation.hpp"
30- #include " runtime/vm_version.hpp"
31- #include " utilities/globalDefinitions.hpp"
32-
3329// Interface for updating the instruction cache. Whenever the VM
3430// modifies code, part of the processor instruction cache potentially
3531// has to be flushed.
@@ -41,103 +37,8 @@ class ICache : public AbstractICache {
4137 __builtin___clear_cache ((char *)addr, (char *)(addr + 4 ));
4238 }
4339 static void invalidate_range (address start, int nbytes) {
44- if (NeoverseN1ICacheErratumMitigation) {
45- assert (VM_Version::is_cache_idc_enabled (),
46- " Expect CTR_EL0.IDC to be enabled for Neoverse N1 with erratum "
47- " 1542419"
48- assert (!VM_Version::is_cache_dic_enabled (),
49- " Expect CTR_EL0.DIC to be disabled for Neoverse N1 with erratum "
50- " 1542419"
51- asm volatile (" dsb ish \n "
52- " ic ivau, xzr \n "
53- " dsb ish \n "
54- " isb \n "
55- : : : " memory"
56- } else {
57- __builtin___clear_cache ((char *)start, (char *)(start + nbytes));
58- }
40+ __builtin___clear_cache ((char *)start, (char *)(start + nbytes));
5941 }
6042};
6143
62- class AArch64ICacheInvalidationContext : StackObj {
63- private:
64-
65- #ifdef ASSERT
66- static THREAD_LOCAL AArch64ICacheInvalidationContext* _current_context;
67- #endif
68-
69- bool _has_modified_code;
70-
71- public:
72- NONCOPYABLE (AArch64ICacheInvalidationContext);
73-
74- AArch64ICacheInvalidationContext ()
75- : _has_modified_code(false ) {
76- assert (_current_context == nullptr , " nested ICacheInvalidationContext not supported"
77- #ifdef ASSERT
78- _current_context = this ;
79- #endif
80- }
81-
82- ~AArch64ICacheInvalidationContext () {
83- NOT_PRODUCT (_current_context = nullptr );
84-
85- if (!_has_modified_code || !UseSingleICacheInvalidation) {
86- return ;
87- }
88-
89- assert (VM_Version::is_cache_idc_enabled (), " Expect CTR_EL0.IDC to be enabled"
90-
91- asm volatile (" dsb ish" " memory"
92-
93- if (NeoverseN1ICacheErratumMitigation) {
94- assert (!VM_Version::is_cache_dic_enabled (),
95- " Expect CTR_EL0.DIC to be disabled for Neoverse N1 with erratum "
96- " 1542419"
97-
98- // Errata 1542419: Neoverse N1 cores with the 'COHERENT_ICACHE' feature
99- // may fetch stale instructions when software depends on
100- // prefetch-speculation-protection instead of explicit synchronization.
101- //
102- // Neoverse-N1 implementation mitigates the errata 1542419 with a
103- // workaround:
104- // - Disable coherent icache.
105- // - Trap IC IVAU instructions.
106- // - Execute:
107- // - tlbi vae3is, xzr
108- // - dsb sy
109- // - Ignore trapped IC IVAU instructions.
110- //
111- // `tlbi vae3is, xzr` invalidates all translation entries (all VAs, all
112- // possible levels). It waits for all memory accesses using in-scope old
113- // translation information to complete before it is considered complete.
114- //
115- // As this workaround has significant overhead, Arm Neoverse N1 (MP050)
116- // Software Developer Errata Notice version 29.0 suggests:
117- //
118- // "Since one TLB inner-shareable invalidation is enough to avoid this
119- // erratum, the number of injected TLB invalidations should be minimized
120- // in the trap handler to mitigate the performance impact due to this
121- // workaround."
122- // As the address for icache invalidation is not relevant and
123- // IC IVAU instruction is ignored, we use XZR in it.
124- asm volatile (
125- " ic ivau, xzr \n "
126- " dsb ish \n "
127- :
128- :
129- : " memory"
130- } else {
131- assert (VM_Version::is_cache_dic_enabled (), " Expect CTR_EL0.DIC to be enabled"
132- }
133- asm volatile (" isb" " memory"
134- }
135-
136- void set_has_modified_code () {
137- _has_modified_code = true ;
138- }
139- };
140-
141- #define PD_ICACHE_INVALIDATION_CONTEXT AArch64ICacheInvalidationContext
142-
14344#endif // OS_CPU_LINUX_AARCH64_ICACHE_AARCH64_HPP
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