Merge pull request #309 from krcb197/hidden_instance_bug_fixes

Hidden instance bug fixes

Author: krcb197

src/peakrdl_python/__about__.py

@@ -17,4 +17,4 @@
 
 Variables that describes the peakrdl-python Package
 """
-__version__ = "3.1.1"
+__version__ = "3.1.2"

src/peakrdl_python/templates/addrmap.py.jinja

@@ -145,7 +145,7 @@ class {{node.python_class_name}}({% if asyncoutput %}Async{% endif %}RegFile):
     {{get_table_block(node.instance) | indent}}
     """
 
-    __slots__ : list[str] = [{%- for child_node in node.instance.children(unroll=False) -%}'__{{child_node.inst_name}}'{% if not loop.last %}, {% endif %}{%- endfor %}]
+    __slots__ : list[str] = [{%- for child_node in node.children(unroll=False) -%}'__{{child_node.inst_name}}'{% if not loop.last %}, {% endif %}{%- endfor %}]
 
     def __init__(self,
                  address: int,
@@ -159,7 +159,7 @@ class {{node.python_class_name}}({% if asyncoutput %}Async{% endif %}RegFile):
                          parent=parent)
 
         # instance of objects within the class
-        {% for child_node in node.instance.children(unroll=False) -%}
+        {% for child_node in node.children(unroll=False) -%}
             {{ regfile_or_addr_instance(child_node) | indent }}
         {% endfor %}
 
@@ -214,7 +214,7 @@ class {{node.python_class_name}}({% if asyncoutput %}Async{% endif %}AddressMap)
     {{get_table_block(node.instance) | indent}}
     """
 
-    __slots__ : list[str] = [{%- for child_node in node.instance.children(unroll=False) -%}{%- if isinstance(child_node, systemrdlRegNode) or isinstance(child_node, systemrdlRegfileNode) or isinstance(child_node, systemrdlAddrmapNode) or isinstance(child_node, systemrdlMemNode) -%}'__{{child_node.inst_name}}'{% if not loop.last %}, {% endif %}{% endif %}{%- endfor %}]
+    __slots__ : list[str] = [{%- for child_node in node.children(unroll=False) -%}{%- if isinstance(child_node, systemrdlRegNode) or isinstance(child_node, systemrdlRegfileNode) or isinstance(child_node, systemrdlAddrmapNode) or isinstance(child_node, systemrdlMemNode) -%}'__{{child_node.inst_name}}'{% if not loop.last %}, {% endif %}{% endif %}{%- endfor %}]
 
     def __init__(self, *,
                  address:int {%- if node.instance == top_node -%}={{top_node.absolute_address}}{%- endif -%},
@@ -233,7 +233,7 @@ class {{node.python_class_name}}({% if asyncoutput %}Async{% endif %}AddressMap)
                          inst_name=inst_name,
                          parent=parent)
 
-        {% for child_node in node.instance.children(unroll=False) -%}
+        {% for child_node in node.children(unroll=False) -%}
             {{ regfile_or_addr_instance(child_node) | indent }}
         {% endfor %}
 

src/peakrdl_python/templates/addrmap_register.py.jinja

@@ -82,7 +82,7 @@ class {{node.python_class_name}}({{node.base_class(asyncoutput)}}):
     {{get_table_block(node.instance) | indent}}
     """
 
-    __slots__ : list[str] = [{%- for child_node in node.instance.children(unroll=False) -%}'__{{child_node.inst_name}}'{% if not loop.last %}, {% endif %}{%- endfor %}]
+    __slots__ : list[str] = [{%- for child_node in node.children(unroll=False) -%}'__{{child_node.inst_name}}'{% if not loop.last %}, {% endif %}{%- endfor %}]
 
     def __init__(self,
                  address: int,
@@ -129,12 +129,12 @@ class {{node.python_class_name}}({{node.base_class(asyncoutput)}}):
 
     {% if node.write_only %}
     {# if the register has no readable components, all the fields must be writen as one #}
-    {% if asyncoutput %}async {% endif %}def write_fields(self, {%- for child_node in node.instance.fields() -%} {{safe_node_name(child_node)}} : {{node.lookup_field_data_python_class(child_node)}}{%- if not loop.last -%},{%- endif -%}{%- endfor -%}) -> None: # type: ignore[override]
+    {% if asyncoutput %}async {% endif %}def write_fields(self, {%- for child_node in node.fields() -%} {{safe_node_name(child_node)}} : {{node.lookup_field_data_python_class(child_node)}}{%- if not loop.last -%},{%- endif -%}{%- endfor -%}) -> None: # type: ignore[override]
         """
         Do a write to the register, updating all fields
         """
         reg_value = 0
-        {%- for child_node in node.instance.fields() %}
+        {%- for child_node in node.fields() %}
         reg_value &= self.{{safe_node_name(child_node)}}.inverse_bitmask
         reg_value |= self.{{safe_node_name(child_node)}}._encode_write_value({{safe_node_name(child_node)}})
         {% endfor %}

tests/testcases/reserved_elements.rdl

@@ -9,6 +9,13 @@ addrmap reserved_elements {
         field { fieldwidth=1; } show;
     };
 
+    reg  {
+        default sw = w;
+        default hw = r;
+        field { fieldwidth=1; } RSVD;
+        field { fieldwidth=1; } field_a;
+    } write_only_register;
+
     reg  {
         default sw = rw;
         default hw = r;