Remove the typecode checking in non-legacy mode

Author: krcb197

src/peakrdl_python/lib_test/_common_base_test_class.py

@@ -175,15 +175,18 @@ def _single_memory_property_test(self, *,
                                      width: int,
                                      entries: int,
                                      accesswidth: Optional[int],
-                                     array_typecode: str) -> None:
+                                     array_typecode: Optional[str]) -> None:
         self.assertEqual(mut.address, address)
         self.assertEqual(mut.width, width)
         self.assertEqual(mut.entries, entries)
         if accesswidth is not None:
             self.assertEqual(mut.accesswidth, accesswidth)
         else:
             self.assertEqual(mut.accesswidth, width)
-        self.assertEqual(mut.array_typecode, array_typecode)
+        if self.legacy_block_access:
+            self.assertEqual(mut.array_typecode, array_typecode)
+        else:
+            self.assertIsNone(array_typecode)
 
     def _single_node_rdl_name_and_desc_test(self,
                                             dut: Base,

src/peakrdl_python/templates/addrmap_tb.py.jinja

@@ -184,7 +184,7 @@ class {{fq_block_name}}_single_access({{top_node.inst_name}}_TestCase): # type:
         """
         {% for node in owned_elements.memories -%}
         with self.subTest(msg='memory: {{'.'.join(node.get_path_segments())}}'):
-            self._single_memory_property_test(mut=self.dut.{{'.'.join(get_python_path_segments(node))}}, address={{node.absolute_address}}, width={{node.get_property('memwidth')}}, entries={{node.get_property('mementries')}}, accesswidth={% if 'accesswidth' in node.list_properties() -%}{{node.get_property('accesswidth')}}{% else %}None{%- endif %}, array_typecode='{{get_array_typecode(node.get_property('memwidth'))}}')
+            self._single_memory_property_test(mut=self.dut.{{'.'.join(get_python_path_segments(node))}}, address={{node.absolute_address}}, width={{node.get_property('memwidth')}}, entries={{node.get_property('mementries')}}, accesswidth={% if 'accesswidth' in node.list_properties() -%}{{node.get_property('accesswidth')}}{% else %}None{%- endif %}, array_typecode={% if legacy_block_access %}'{{get_array_typecode(node.get_property('memwidth'))}}'{% else %}None{% endif %})
             {% if asyncoutput %}await {%endif %}self._single_memory_read_and_write_test(mut=self.dut.{{'.'.join(get_python_path_segments(node))}}, is_sw_readable={{node.is_sw_readable}}, is_sw_writable={{node.is_sw_writable}},
                                                                                         writeable_registers=NodeIterators( {%- for child_node in node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_writable %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endif %}{% endfor %}),
                                                                                         readable_registers=NodeIterators( {%- for child_node in node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_readable %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endif %}{% endfor %}))