Merge pull request #273 from krcb197/267-make-a-generalised-memory-test_from_r3

Generalised memory test in the library
Closes #267

Author: krcb197

src/peakrdl_python/lib/async_memory.py

@@ -377,6 +377,10 @@ async def _write(self, start_entry: int, data: Union[Array, list[int]]) -> None:
         if not isinstance(data, (list, Array)):
             raise TypeError(f'data should be an array.array got {type(data)}')
 
+        if (max(data) > self.max_entry_value) or (min(data) < 0):
+            raise ValueError('Data out of range for memory must be in the '
+                             f'range 0 to {self.max_entry_value}')
+
         if len(data) not in range(0, self.entries - start_entry + 1):
             raise ValueError(f'data length must be in range 0 to {self.entries - start_entry:d} '
                              f'but got {len(data):d}')

src/peakrdl_python/lib/memory.py

@@ -99,6 +99,20 @@ def width(self) -> int:
         """
         return self.__memwidth
 
+    @property
+    def max_entry_value(self) -> int:
+        """
+        maximum unsigned integer value that can be stored in a memory entry
+
+        For example:
+
+        * 8-bit memory width returns 0xFF (255)
+        * 16-bit memory width returns 0xFFFF (65535)
+        * 32-bit memory width returns 0xFFFF_FFFF (4294967295)
+
+        """
+        return (2 ** self.width) - 1
+
     @property
     def width_in_bytes(self) -> int:
         """
@@ -505,6 +519,10 @@ def _write(self, start_entry: int, data: Union[Array, list[int]]) -> None:
         if not isinstance(data, (Array, list)):
             raise TypeError(f'data should be an List or array.array got {type(data)}')
 
+        if (max(data) > self.max_entry_value) or (min(data) < 0):
+            raise ValueError('Data out of range for memory must be in the '
+                             f'range 0 to {self.max_entry_value}')
+
         if len(data) not in range(0, self.entries - start_entry + 1):
             raise ValueError(f'data length must be in range 0 to {self.entries - start_entry:d} '
                              f'but got {len(data):d}')

src/peakrdl_python/lib/utility_functions.py

@@ -59,7 +59,7 @@ def get_array_typecode(width: int) -> str:
         return 'Q'
 
     if width == 16:
-        return 'I'
+        return 'H'
 
     if width == 8:
         return 'B'

src/peakrdl_python/lib_test/_common_base_test_class.py

@@ -31,6 +31,7 @@
 from ..lib import RegAsyncReadOnly, RegAsyncReadWrite, RegAsyncWriteOnly
 from ..lib import AddressMap, AsyncAddressMap
 from ..lib import RegFile, AsyncRegFile
+from ..lib.memory import BaseMemory
 from ..lib import MemoryReadOnly, MemoryReadOnlyLegacy
 from ..lib import MemoryWriteOnly, MemoryWriteOnlyLegacy
 from ..lib import MemoryReadWrite, MemoryReadWriteLegacy
@@ -95,6 +96,13 @@ def simulator_instance(self) -> BaseSimulator:
         Simulator configured for the DUT
         """
 
+    @property
+    @abstractmethod
+    def legacy_block_access(self) -> bool:
+        """
+        Whether the register model has been configured for legacy block access or not
+        """
+
     # pylint:disable-next=too-many-arguments
     def _single_field_property_test(self, *,
                                     fut: Union[FieldReadWrite,
@@ -160,6 +168,26 @@ def _single_register_property_test(self, *,
         else:
             self.assertEqual(rut.accesswidth, width)
 
+    # pylint:disable-next=too-many-arguments
+    def _single_memory_property_test(self, *,
+                                     mut: BaseMemory,
+                                     address: int,
+                                     width: int,
+                                     entries: int,
+                                     accesswidth: Optional[int],
+                                     array_typecode: Optional[str]) -> None:
+        self.assertEqual(mut.address, address)
+        self.assertEqual(mut.width, width)
+        self.assertEqual(mut.entries, entries)
+        if accesswidth is not None:
+            self.assertEqual(mut.accesswidth, accesswidth)
+        else:
+            self.assertEqual(mut.accesswidth, width)
+        if self.legacy_block_access:
+            self.assertEqual(mut.array_typecode, array_typecode)
+        else:
+            self.assertIsNone(array_typecode)
+
     def _single_node_rdl_name_and_desc_test(self,
                                             dut: Base,
                                             rdl_name: Optional[str],
@@ -190,11 +218,11 @@ def _test_node_inst_name(self,
 
     def _test_field_iterators(self, *,
                               rut: Union[RegReadOnly,
-                                            RegReadWrite,
-                                            RegWriteOnly,
-                                            RegAsyncReadOnly,
-                                            RegAsyncReadWrite,
-                                            RegAsyncWriteOnly],
+                                         RegReadWrite,
+                                         RegWriteOnly,
+                                         RegAsyncReadOnly,
+                                         RegAsyncReadWrite,
+                                         RegAsyncWriteOnly],
                               has_sw_readable: bool,
                               has_sw_writable: bool,
                               readable_fields: set[str],