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Merge pull request #266 from krcb197/258-optimise-test_traversal_iterators
Optimise traversal iterators
2 parents a418d4c + 7c1d488 commit d9d2263

6 files changed

Lines changed: 202 additions & 288 deletions

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‎src/peakrdl_python/lib_test/_common_base_test_class.py‎

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,16 @@
2626
from ..lib import FieldEnumReadWrite, FieldEnumReadOnly, FieldEnumWriteOnly
2727
from ..lib import FieldAsyncReadOnly, FieldAsyncWriteOnly, FieldAsyncReadWrite
2828
from ..lib import FieldEnumAsyncReadOnly, FieldEnumAsyncWriteOnly, FieldEnumAsyncReadWrite
29+
from ..lib import RegReadOnly, RegReadWrite, RegWriteOnly
30+
from ..lib import RegAsyncReadOnly, RegAsyncReadWrite, RegAsyncWriteOnly
31+
from ..lib import AddressMap, AsyncAddressMap
32+
from ..lib import RegFile, AsyncRegFile
33+
from ..lib import MemoryReadOnly, MemoryReadOnlyLegacy
34+
from ..lib import MemoryWriteOnly, MemoryWriteOnlyLegacy
35+
from ..lib import MemoryReadWrite, MemoryReadWriteLegacy
36+
from ..lib import MemoryAsyncReadOnly, MemoryAsyncReadOnlyLegacy
37+
from ..lib import MemoryAsyncWriteOnly, MemoryAsyncWriteOnlyLegacy
38+
from ..lib import MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy
2939
from ..lib.base_register import BaseReg
3040
from ..lib import Base
3141
from .utilities import get_field_bitmask_int, get_field_inv_bitmask
@@ -136,3 +146,124 @@ def _test_node_inst_name(self,
136146
self.assertEqual(dut.inst_name, inst_name)
137147
full_inst_name = parent_full_inst_name + '.' + inst_name
138148
self.assertEqual(dut.full_inst_name, full_inst_name)
149+
150+
def _test_field_iterators(self, *,
151+
rut: Union[RegReadOnly,
152+
RegReadWrite,
153+
RegWriteOnly,
154+
RegAsyncReadOnly,
155+
RegAsyncReadWrite,
156+
RegAsyncWriteOnly],
157+
has_sw_readable: bool,
158+
has_sw_writable: bool,
159+
readable_fields: set[str],
160+
writeable_fields: set[str]) -> None:
161+
if has_sw_readable:
162+
if not isinstance(rut, (RegReadOnly,
163+
RegReadWrite,
164+
RegAsyncReadOnly,
165+
RegAsyncReadWrite,
166+
)):
167+
raise TypeError(f'Register was expected to readable, got {type(rut)}')
168+
169+
child_readable_field_names = { field.inst_name for field in rut.readable_fields}
170+
171+
self.assertEqual(readable_fields, child_readable_field_names)
172+
else:
173+
self.assertFalse(hasattr(rut, 'readable_fields'))
174+
# check the readable_fields is empty
175+
self.assertFalse(readable_fields)
176+
177+
if has_sw_writable:
178+
if not isinstance(rut, (RegWriteOnly,
179+
RegReadWrite,
180+
RegAsyncWriteOnly,
181+
RegAsyncReadWrite,
182+
)):
183+
raise TypeError(f'Register was expected to writable, got {type(rut)}')
184+
185+
child_writeable_fields_names = {field.inst_name for field in rut.writable_fields}
186+
187+
self.assertEqual(writeable_fields, child_writeable_fields_names)
188+
else:
189+
self.assertFalse(hasattr(rut, 'writeable_fields'))
190+
# check the writeable_fields is empty
191+
self.assertFalse(writeable_fields)
192+
193+
child_field_names = {field.inst_name for field in rut.fields}
194+
self.assertEqual(readable_fields | writeable_fields, child_field_names)
195+
196+
def _test_register_iterators(self,
197+
dut: Union[AddressMap, AsyncAddressMap, RegFile, AsyncRegFile,
198+
MemoryReadOnly, MemoryReadOnlyLegacy,
199+
MemoryWriteOnly, MemoryWriteOnlyLegacy,
200+
MemoryReadWrite, MemoryReadWriteLegacy,
201+
MemoryAsyncReadOnly, MemoryAsyncReadOnlyLegacy,
202+
MemoryAsyncWriteOnly, MemoryAsyncWriteOnlyLegacy,
203+
MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy],
204+
readable_registers: set[str],
205+
writeable_registers: set[str]) -> None:
206+
207+
if isinstance(dut, (AddressMap, AsyncAddressMap, RegFile, AsyncRegFile,
208+
MemoryReadOnly, MemoryReadOnlyLegacy,
209+
MemoryReadWrite, MemoryReadWriteLegacy,
210+
MemoryAsyncReadOnly, MemoryAsyncReadOnlyLegacy,
211+
MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy)):
212+
child_readable_reg_names = { reg.inst_name for reg in
213+
dut.get_readable_registers(unroll=True)}
214+
self.assertEqual(readable_registers, child_readable_reg_names)
215+
else:
216+
self.assertFalse(hasattr(dut, 'get_readable_registers'))
217+
218+
if isinstance(dut, (AddressMap, AsyncAddressMap, RegFile, AsyncRegFile,
219+
MemoryWriteOnly, MemoryWriteOnlyLegacy,
220+
MemoryReadWrite, MemoryReadWriteLegacy,
221+
MemoryAsyncWriteOnly, MemoryAsyncWriteOnlyLegacy,
222+
MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy)):
223+
child_writable_reg_names = {reg.inst_name for reg in
224+
dut.get_writable_registers(unroll=True)}
225+
self.assertEqual(writeable_registers, child_writable_reg_names)
226+
else:
227+
self.assertFalse(hasattr(dut, 'get_writable_registers'))
228+
229+
child_reg_names = {field.inst_name for field in dut.get_registers(unroll=True)}
230+
self.assertEqual(readable_registers | writeable_registers, child_reg_names)
231+
232+
233+
def _test_memory_iterators(self,
234+
dut: Union[AddressMap, AsyncAddressMap],
235+
memories: set[str]) -> None:
236+
child_mem_names = {reg.inst_name for reg in dut.get_memories(unroll=True)}
237+
self.assertEqual(memories, child_mem_names)
238+
239+
def __test_section_iterators(self,
240+
dut: Union[AddressMap, AsyncAddressMap, RegFile, AsyncRegFile],
241+
sections: set[str]) -> None:
242+
child_section_names = {reg.inst_name for reg in dut.get_sections(unroll=True)}
243+
self.assertEqual(sections, child_section_names)
244+
245+
def _test_addrmap_iterators(self, *,
246+
dut: Union[AddressMap, AsyncAddressMap],
247+
memories: set[str],
248+
sections: set[str],
249+
readable_registers: set[str],
250+
writeable_registers: set[str]) -> None:
251+
self._test_register_iterators(dut=dut,
252+
readable_registers=readable_registers,
253+
writeable_registers=writeable_registers)
254+
self._test_memory_iterators(dut=dut,
255+
memories=memories)
256+
self.__test_section_iterators(dut=dut,
257+
sections=sections)
258+
259+
def _test_regfile_iterators(self,
260+
dut: Union[RegFile, AsyncRegFile],
261+
sections: set[str],
262+
readable_registers: set[str],
263+
writeable_registers: set[str]) -> None:
264+
self._test_register_iterators(dut=dut,
265+
readable_registers=readable_registers,
266+
writeable_registers=writeable_registers)
267+
self.__test_section_iterators(dut=dut,
268+
sections=sections)
269+
self.assertFalse(hasattr(dut, 'get_memories'))

‎src/peakrdl_python/lib_test/async_reg_base_test_class.py‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -318,13 +318,21 @@ async def _single_enum_field_read_and_write_test(
318318
enum_definition=enum_definition)
319319

320320
async def _single_register_read_and_write_test(
321-
self,
321+
self, *,
322322
rut: Union[RegAsyncReadOnly, RegAsyncReadWrite, RegAsyncWriteOnly],
323323
has_sw_readable: bool,
324-
has_sw_writable: bool) -> None:
324+
has_sw_writable: bool,
325+
readable_fields: set[str],
326+
writeable_fields: set[str]) -> None:
325327

326328
# the register properties are tested separately so are available to be used here
327329

330+
self._test_field_iterators(rut=rut,
331+
has_sw_readable=has_sw_readable,
332+
has_sw_writable=has_sw_writable,
333+
readable_fields=readable_fields,
334+
writeable_fields=writeable_fields)
335+
328336
await self.__single_register_simulator_read_and_write_test(
329337
rut=rut,
330338
has_sw_readable=has_sw_readable,

‎src/peakrdl_python/lib_test/base_reg_test_class.py‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -309,13 +309,21 @@ def _single_enum_field_read_and_write_test(
309309
self.__single_enum_field_write_test(fut=fut,
310310
enum_definition=enum_definition)
311311

312-
def _single_register_read_and_write_test(self,
312+
def _single_register_read_and_write_test(self, *,
313313
rut: Union[RegReadOnly, RegReadWrite, RegWriteOnly],
314314
has_sw_readable: bool,
315-
has_sw_writable: bool) -> None:
315+
has_sw_writable: bool,
316+
readable_fields: set[str],
317+
writeable_fields: set[str]) -> None:
316318

317319
# the register properties are tested separately so are available to be used here
318320

321+
self._test_field_iterators(rut=rut,
322+
has_sw_readable=has_sw_readable,
323+
has_sw_writable=has_sw_writable,
324+
readable_fields=readable_fields,
325+
writeable_fields=writeable_fields)
326+
319327
self.__single_register_simulator_read_and_write_test(rut=rut,
320328
has_sw_readable=has_sw_readable,
321329
has_sw_writable=has_sw_writable)

‎src/peakrdl_python/templates/addrmap_register.py.jinja‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ class {{node.python_class_name}}({{node.base_class(asyncoutput)}}):
9393
Memory{% if asyncoutput %}Async{% endif -%}ReadWrite{% if legacy_block_access %}Legacy{% endif %}
9494
{%- elif node.read_only -%}
9595
Readable{% if asyncoutput %}Async{% endif -%}Memory{% if legacy_block_access %}Legacy{% endif %}
96-
{%- elif node.read_only -%}
96+
{%- elif node.write_only -%}
9797
Writable{% if asyncoutput %}Async{% endif -%}Memory{% if legacy_block_access %}Legacy{% endif %}
9898
{%- endif -%}
9999
]):

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