Update to the iterator test:

- Only list out the names of the rolled up forms, this simplifies arrays
- test both the rolled and unrolled iterators

Author: krcb197

src/peakrdl_python/exporter.py

@@ -46,7 +46,8 @@
     get_memory_max_entry_value_hex_string, get_memory_width_bytes, \
     get_field_default_value, get_enum_values, get_properties_to_include, \
     HideNodeCallback, hide_based_on_property, \
-    full_slice_accessor, ShowUDPCallback
+    full_slice_accessor, ShowUDPCallback, \
+    node_iterator_entry
 from .unique_component_iterator import UniqueComponents
 from .unique_component_iterator import PeakRDLPythonUniqueRegisterComponents
 from .unique_component_iterator import PeakRDLPythonUniqueMemoryComponents
@@ -865,7 +866,8 @@ def is_reg_node(node: Node) -> TypeGuard[RegNode]:
                 'get_properties_to_include': get_properties_to_include,
                 'hide_node_func': hide_node_func,
                 'legacy_enum_type': legacy_enum_type,
-                'skip_systemrdl_name_and_desc_properties': skip_systemrdl_name_and_desc_properties
+                'skip_systemrdl_name_and_desc_properties': skip_systemrdl_name_and_desc_properties,
+                'node_iterator_entry': node_iterator_entry,
             }
 
             self.__stream_jinja_template(template_name="addrmap_tb.py.jinja",

src/peakrdl_python/lib_test/__init__.py

@@ -22,3 +22,5 @@
 from .async_reg_base_test_class import AsyncLibTestBase
 
 from .utilities import reverse_bits
+
+from ._common_base_test_class import NodeIterators

src/peakrdl_python/lib_test/_common_base_test_class.py

@@ -21,6 +21,7 @@
 import unittest
 from abc import ABC, abstractmethod
 from typing import Union, Optional
+from itertools import product
 
 from ..lib import FieldReadWrite, FieldReadOnly, FieldWriteOnly
 from ..lib import FieldEnumReadWrite, FieldEnumReadOnly, FieldEnumWriteOnly
@@ -41,6 +42,46 @@
 from .utilities import get_field_bitmask_int, get_field_inv_bitmask
 from ..sim_lib.simulator import BaseSimulator
 
+class NodeIterators:
+    """
+    The Node Iterator class is intended to an efficient way to define the iterators of particular
+    type that are present on a node
+    """
+    __slots__ = ['__node_descriptions']
+    def __init__(self, *args:Union[str, tuple[str, list[int]]]):
+        self.__node_descriptions = args
+
+    @staticmethod
+    def __rolled_item(item:Union[str, tuple[str, list[int]]]) -> str:
+        if isinstance(item, tuple):
+            return item[0]
+        return item
+
+    @property
+    def rolled(self) -> set[str]:
+        """
+        name of all the rolled nodes in a set
+        """
+        return { self.__rolled_item(item) for item in self.__node_descriptions }
+
+    @property
+    def unrolled(self) -> set[str]:
+        """
+        name of all the unrolled nodes in a set
+        """
+        return_list = []
+        for item in self.__node_descriptions:
+            if isinstance(item, tuple):
+                dim_set =  list(product(*[range(dim) for dim in item[1]]))
+                for dim in dim_set:
+                    # to match the systemrdl compiler dimension put into the inst name of
+                    # the array, the name must be item[x][y]
+                    dim_str = ''.join([f'[{str(i)}]' for i in dim])
+                    return_list.append(f'{item[0]}{dim_str}')
+            else:
+                return_list.append(item)
+        return set(return_list)
+
 class CommonTestBase(unittest.TestCase, ABC):
     """
     Base Test class for the autogenerated register test to be used for the async and
@@ -201,8 +242,8 @@ def _test_register_iterators(self,
                                             MemoryAsyncReadOnly, MemoryAsyncReadOnlyLegacy,
                                             MemoryAsyncWriteOnly, MemoryAsyncWriteOnlyLegacy,
                                             MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy],
-                                 readable_registers: set[str],
-                                 writeable_registers: set[str]) -> None:
+                                 readable_registers: NodeIterators,
+                                 writeable_registers: NodeIterators) -> None:
 
         if isinstance(dut, (AddressMap, AsyncAddressMap, RegFile, AsyncRegFile,
                             MemoryReadOnly, MemoryReadOnlyLegacy,
@@ -211,7 +252,10 @@ def _test_register_iterators(self,
                             MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy)):
             child_readable_reg_names = { reg.inst_name for reg in
                                          dut.get_readable_registers(unroll=True)}
-            self.assertEqual(readable_registers, child_readable_reg_names)
+            self.assertEqual(readable_registers.unrolled, child_readable_reg_names)
+            child_readable_reg_names = {reg.inst_name for reg in
+                                        dut.get_readable_registers(unroll=False)}
+            self.assertEqual(readable_registers.rolled, child_readable_reg_names)
         else:
             self.assertFalse(hasattr(dut, 'get_readable_registers'))
 
@@ -222,32 +266,43 @@ def _test_register_iterators(self,
                             MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy)):
             child_writable_reg_names = {reg.inst_name for reg in
                                         dut.get_writable_registers(unroll=True)}
-            self.assertEqual(writeable_registers, child_writable_reg_names)
+            self.assertEqual(writeable_registers.unrolled, child_writable_reg_names)
+            child_writable_reg_names = {reg.inst_name for reg in
+                                        dut.get_writable_registers(unroll=False)}
+            self.assertEqual(writeable_registers.rolled, child_writable_reg_names)
         else:
             self.assertFalse(hasattr(dut, 'get_writable_registers'))
 
         child_reg_names = {field.inst_name for field in dut.get_registers(unroll=True)}
-        self.assertEqual(readable_registers | writeable_registers, child_reg_names)
+        self.assertEqual(readable_registers.unrolled | writeable_registers.unrolled,
+                         child_reg_names)
+        child_reg_names = {field.inst_name for field in dut.get_registers(unroll=False)}
+        self.assertEqual(readable_registers.rolled | writeable_registers.rolled,
+                         child_reg_names)
 
 
     def _test_memory_iterators(self,
                                dut: Union[AddressMap, AsyncAddressMap],
-                               memories: set[str]) -> None:
+                               memories: NodeIterators) -> None:
         child_mem_names = {reg.inst_name for reg in dut.get_memories(unroll=True)}
-        self.assertEqual(memories, child_mem_names)
+        self.assertEqual(memories.unrolled, child_mem_names)
+        child_mem_names = {reg.inst_name for reg in dut.get_memories(unroll=False)}
+        self.assertEqual(memories.rolled, child_mem_names)
 
     def __test_section_iterators(self,
                                  dut: Union[AddressMap, AsyncAddressMap, RegFile, AsyncRegFile],
-                                 sections: set[str]) -> None:
+                                 sections: NodeIterators) -> None:
         child_section_names = {reg.inst_name for reg in dut.get_sections(unroll=True)}
-        self.assertEqual(sections, child_section_names)
+        self.assertEqual(sections.unrolled, child_section_names)
+        child_section_names = {reg.inst_name for reg in dut.get_sections(unroll=False)}
+        self.assertEqual(sections.rolled, child_section_names)
 
     def _test_addrmap_iterators(self, *,
                                 dut: Union[AddressMap, AsyncAddressMap],
-                                memories: set[str],
-                                sections: set[str],
-                                readable_registers: set[str],
-                                writeable_registers: set[str]) -> None:
+                                memories: NodeIterators,
+                                sections: NodeIterators,
+                                readable_registers: NodeIterators,
+                                writeable_registers: NodeIterators) -> None:
         self._test_register_iterators(dut=dut,
                                       readable_registers=readable_registers,
                                       writeable_registers=writeable_registers)
@@ -258,9 +313,9 @@ def _test_addrmap_iterators(self, *,
 
     def _test_regfile_iterators(self,
                                 dut: Union[RegFile, AsyncRegFile],
-                                sections: set[str],
-                                readable_registers: set[str],
-                                writeable_registers: set[str]) -> None:
+                                sections: NodeIterators,
+                                readable_registers: NodeIterators,
+                                writeable_registers: NodeIterators) -> None:
         self._test_register_iterators(dut=dut,
                                       readable_registers=readable_registers,
                                       writeable_registers=writeable_registers)

src/peakrdl_python/systemrdl_node_utility_functions.py

@@ -480,3 +480,18 @@ def full_slice_accessor(node: AddressableNode) -> str:
     if dimensions is None:
         raise RuntimeError('array node should have dimensions')
     return '[' + ','.join([':' for _ in range(len(dimensions))]) + ']'
+
+def node_iterator_entry(node: AddressableNode) -> str:
+    """
+    The NodeIterators in the lib_test requires all the children of a node to be presented in the
+    following format:
+    - non-array node: str of the name inst name from the system RDL
+    - array node: a tuple with the inst name and the length
+    """
+    if node.is_array:
+        dimensions = node.array_dimensions
+        if dimensions is None:
+            raise RuntimeError('array node should have dimensions')
+        return f"('{node.inst_name}', {str(dimensions)})"
+
+    return "'" + node.inst_name + "'"

src/peakrdl_python/templates/addrmap_tb.py.jinja

@@ -75,6 +75,7 @@ from {{ peakrdl_python_lib(depth=lib_depth) }} import Reg
 from {{ peakrdl_python_lib(depth=lib_depth) }} import SystemRDLEnum, SystemRDLEnumEntry
 {% endif %}
 from {{ peakrdl_python_lib_test(depth=lib_depth) }} import reverse_bits
+from {{ peakrdl_python_lib_test(depth=lib_depth) }} import NodeIterators
 
 from ._{{top_node.inst_name}}_test_base import {{top_node.inst_name}}_TestCase, {{top_node.inst_name}}_TestCase_BlockAccess, {{top_node.inst_name}}_TestCase_AltBlockAccess
 from ._{{top_node.inst_name}}_test_base import __name__ as base_name
@@ -345,10 +346,10 @@ class {{fq_block_name}}_single_access({{top_node.inst_name}}_TestCase): # type:
     def test_top_traversal_iterators(self) -> None:
 
         self._test_addrmap_iterators(dut=self.dut,
-                                     writeable_registers=set([ {%- for child_node in top_node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_writable %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endif %}{% endfor %} ]),
-                                     readable_registers=set([ {%- for child_node in top_node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_readable %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endif %}{% endfor %} ]),
-                                     sections=set([ {%- for child_node in top_node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, (systemrdlRegfileNode,systemrdlAddrmapNode)) %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endfor %} ]),
-                                     memories=set([ {%- for child_node in top_node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlMemNode) %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endfor %} ]))
+                                     writeable_registers=NodeIterators({%- for child_node in top_node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_writable %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endif %}{% endfor %}),
+                                     readable_registers=NodeIterators({%- for child_node in top_node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_readable %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endif %}{% endfor %}),
+                                     sections=NodeIterators({%- for child_node in top_node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, (systemrdlRegfileNode,systemrdlAddrmapNode)) %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endfor %}),
+                                     memories=NodeIterators({%- for child_node in top_node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlMemNode) %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endfor %}))
 
     {% endif %}{# if block == top_block #}
 
@@ -363,25 +364,25 @@ class {{fq_block_name}}_single_access({{top_node.inst_name}}_TestCase): # type:
         {% for node in owned_elements.memories -%}
         with self.subTest(msg='memory: {{'.'.join(node.get_path_segments())}}'):
             self._test_register_iterators(dut=self.dut.{{'.'.join(get_python_path_segments(node))}},
-                                          writeable_registers=set([ {%- for child_node in node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_writable %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endif %}{% endfor %} ]),
-                                          readable_registers=set([ {%- for child_node in node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_readable %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endif %}{% endfor %} ]))
+                                          writeable_registers=NodeIterators( {%- for child_node in node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_writable %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endif %}{% endfor %}),
+                                          readable_registers=NodeIterators( {%- for child_node in node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_readable %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endif %}{% endfor %}))
         {% endfor %}
         # test all the address maps
         {% for node in owned_elements.addr_maps -%}
         with self.subTest(msg='addrmap: {{'.'.join(node.get_path_segments())}}'):
             self._test_addrmap_iterators(dut=self.dut.{{'.'.join(get_python_path_segments(node))}},
-                                         writeable_registers=set([ {%- for child_node in node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_writable %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endif %}{% endfor %} ]),
-                                         readable_registers=set([ {%- for child_node in node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_readable %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endif %}{% endfor %} ]),
-                                         sections=set([ {%- for child_node in node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, (systemrdlRegfileNode,systemrdlAddrmapNode)) %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endfor %} ]),
-                                         memories=set([ {%- for child_node in node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlMemNode) %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endfor %} ]))
+                                         writeable_registers=NodeIterators( {%- for child_node in node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_writable %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endif %}{% endfor %}),
+                                         readable_registers=NodeIterators( {%- for child_node in node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_readable %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endif %}{% endfor %}),
+                                         sections=NodeIterators( {%- for child_node in node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, (systemrdlRegfileNode,systemrdlAddrmapNode)) %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endfor %}),
+                                         memories=NodeIterators( {%- for child_node in node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlMemNode) %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endfor %}))
         {% endfor %}
         # test all the register files
         {% for node in owned_elements.reg_files -%}
         with self.subTest(msg='regfile: {{'.'.join(node.get_path_segments())}}'):
             self._test_regfile_iterators(dut=self.dut.{{'.'.join(get_python_path_segments(node))}},
-                                         writeable_registers=set([ {%- for child_node in node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_writable %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endif %}{% endfor %} ]),
-                                         readable_registers=set([ {%- for child_node in node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_readable %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endif %}{% endfor %} ]),
-                                         sections=set([ {%- for child_node in node.children(unroll=True) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, (systemrdlRegfileNode,systemrdlAddrmapNode)) %}'{{child_node.get_path_segments()[-1]}}',{% endif %}{% endif %}{% endfor %} ]))
+                                         writeable_registers=NodeIterators({%- for child_node in node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_writable %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endif %}{% endfor %}),
+                                         readable_registers=NodeIterators({%- for child_node in node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, systemrdlRegNode) %}{% if child_node.has_sw_readable %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endif %}{% endfor %}),
+                                         sections=NodeIterators({%- for child_node in node.children(unroll=False) %}{%- if not hide_node_func(child_node) %}{%- if isinstance(child_node, (systemrdlRegfileNode,systemrdlAddrmapNode)) %}{{node_iterator_entry(child_node)}},{% endif %}{% endif %}{% endfor %}))
         {% endfor %}
 
     def test_name_map(self) -> None: