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Commit 3d87085

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ccj
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[linux_boot] 启动了linux但是还没有资源互斥
1 parent c4205f3 commit 3d87085

8 files changed

Lines changed: 750 additions & 13 deletions

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‎bsp/qemu-virt64-aarch64/Image‎

21.6 MB
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‎bsp/qemu-virt64-aarch64/applications/SConscript‎

Lines changed: 1 addition & 1 deletion
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@@ -1,7 +1,7 @@
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp')
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src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
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CPPPATH = [cwd]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)

‎bsp/qemu-virt64-aarch64/applications/linux_boot.c‎

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/*
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* Boot the reserved CPU3 into the Linux Image loaded by xqemu.bat.
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*/
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#include <rtthread.h>
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#include <cache.h>
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#include <cpuport.h>
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#include <hypercall.h>
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#include <mm_aspace.h>
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#include <mmu.h>
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#include <psci.h>
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#define LINUX_CPU3_MPIDR 0x3UL
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#define LINUX_IMAGE_ENTRY 0x48200000UL
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#define LINUX_DTB_ADDRESS 0x4f000000UL
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extern void linux_cpu3_trampoline(void);
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extern char linux_cpu3_trampoline_end[];
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static int linux_boot(int argc, char **argv)
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{
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rt_uint32_t ret;
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rt_size_t trampoline_size;
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rt_ubase_t trampoline_pa;
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RT_UNUSED(argc);
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RT_UNUSED(argv);
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trampoline_size = (rt_ubase_t)linux_cpu3_trampoline_end - (rt_ubase_t)linux_cpu3_trampoline;
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trampoline_pa = (rt_ubase_t)rt_kmem_v2p((void *)linux_cpu3_trampoline);
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if ((void *)trampoline_pa == ARCH_MAP_FAILED)
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{
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rt_kprintf("linux_boot: trampoline v2p failed\n");
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return -RT_ERROR;
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}
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rt_hw_cpu_dcache_clean((void *)linux_cpu3_trampoline, trampoline_size);
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rt_hw_icache_invalidate_all();
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rt_hw_dsb();
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rt_hw_isb();
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rt_kprintf("linux_boot: cpu3 mpidr=0x%lx trampoline=0x%lx image=0x%lx dtb=0x%lx\n",
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LINUX_CPU3_MPIDR, trampoline_pa, LINUX_IMAGE_ENTRY, LINUX_DTB_ADDRESS);
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ret = rt_hv_cpu_on(LINUX_CPU3_MPIDR, trampoline_pa, 0);
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rt_kprintf("linux_boot: HYP CPU_ON returned %d\n", (int)ret);
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return ret == PSCI_RET_SUCCESS ? RT_EOK : -RT_ERROR;
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}
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MSH_CMD_EXPORT(linux_boot, boot Linux on reserved CPU3);

‎bsp/qemu-virt64-aarch64/applications/linux_trampoline.S‎

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/*
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* Trampoline for booting a Linux Image on a reserved CPU.
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#define LINUX_IMAGE_ENTRY 0x48200000
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#define LINUX_DTB_ADDRESS 0x4f000000
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.section ".text.linux_trampoline", "ax"
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.align 6
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.global linux_cpu3_trampoline
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linux_cpu3_trampoline:
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ldr x0, =LINUX_DTB_ADDRESS
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mov x1, xzr
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mov x2, xzr
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mov x3, xzr
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ldr x4, =LINUX_IMAGE_ENTRY
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br x4
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.global linux_cpu3_trampoline_end
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linux_cpu3_trampoline_end:

‎bsp/qemu-virt64-aarch64/linux.dts‎

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/dts-v1/;
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/ {
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interrupt-parent = <0x8005>;
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dma-coherent;
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model = "linux,virt-isolated";
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compatible = "linux,dummy-virt";
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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psci {
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migrate = <0xc4000005>;
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cpu_on = <0xc4000003>;
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cpu_off = <0x84000002>;
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cpu_suspend = <0xc4000001>;
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method = "smc";
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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};
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memory@48000000 {
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device_type = "memory";
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reg = <0x00 0x48000000 0x00 0x08000000>;
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};
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virtio_mmio@a000000 {
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dma-coherent;
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interrupts = <0x00 0x10 0x01>;
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reg = <0x00 0xa000000 0x00 0x200>;
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compatible = "virtio,mmio";
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};
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intc: intc@8000000 {
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phandle = <0x8005>;
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interrupts = <0x01 0x09 0x04>;
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reg = <0x00 0x8000000 0x00 0x10000 0x00 0x8010000 0x00 0x10000 0x00 0x8030000 0x00 0x10000 0x00 0x8040000 0x00 0x10000>;
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compatible = "arm,cortex-a15-gic";
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ranges;
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#size-cells = <0x02>;
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#address-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x03>;
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};
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cpus {
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#size-cells = <0x00>;
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#address-cells = <0x01>;
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cpu-map {
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socket0 {
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cluster0 {
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core0 { cpu = <0x8001>; };
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};
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};
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};
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cpu@3 {
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phandle = <0x8001>;
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reg = <0x03>;
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enable-method = "psci";
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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};
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};
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timer {
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interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>;
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always-on;
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compatible = "arm,armv8-timer", "arm,armv7-timer";
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};
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chosen {
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bootargs = "console=hvc0 maxcpus=1 nr_cpus=1 loglevel=8";
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};
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};

‎bsp/qemu-virt64-aarch64/rtt.dts‎

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/dts-v1/;
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/ {
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interrupt-parent = <0x8005>;
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dma-coherent;
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model = "rtt,virt";
7+
compatible = "linux,dummy-virt";
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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psci {
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migrate = <0xc4000005>;
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cpu_on = <0xc4000003>;
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cpu_off = <0x84000002>;
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cpu_suspend = <0xc4000001>;
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method = "smc";
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x00 0x40000000 0x00 0x08000000>;
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};
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pl011@9000000 {
26+
clock-names = "uartclk", "apb_pclk";
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clocks = <&apb_pclk &apb_pclk>;
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interrupts = <0x00 0x01 0x04>;
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reg = <0x00 0x9000000 0x00 0x1000>;
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compatible = "arm,pl011", "arm,primecell";
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};
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intc: intc@8000000 {
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phandle = <0x8005>;
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interrupts = <0x01 0x09 0x04>;
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reg = <0x00 0x8000000 0x00 0x10000 0x00 0x8010000 0x00 0x10000 0x00 0x8030000 0x00 0x10000 0x00 0x8040000 0x00 0x10000>;
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compatible = "arm,cortex-a15-gic";
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ranges;
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#size-cells = <0x02>;
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#address-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x03>;
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};
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cpus {
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#size-cells = <0x00>;
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#address-cells = <0x01>;
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cpu-map {
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socket0 {
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cluster0 {
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core0 { cpu = <0x8004>; };
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core1 { cpu = <0x8003>; };
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core2 { cpu = <0x8002>; };
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};
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};
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};
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cpu@0 {
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phandle = <0x8004>;
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reg = <0x00>;
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enable-method = "psci";
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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};
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cpu@1 {
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phandle = <0x8003>;
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reg = <0x01>;
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enable-method = "psci";
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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};
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cpu@2 {
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phandle = <0x8002>;
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reg = <0x02>;
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enable-method = "psci";
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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};
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};
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timer {
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interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>;
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always-on;
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compatible = "arm,armv8-timer", "arm,armv7-timer";
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};
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apb_pclk: apb-pclk {
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clock-output-names = "clk24mhz";
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clock-frequency = <0x16e3600>;
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#clock-cells = <0x00>;
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compatible = "fixed-clock";
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};
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aliases {
98+
serial0 = "/pl011@9000000";
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};
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chosen {
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stdout-path = "/pl011@9000000";
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};
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};

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