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LATX, opt: Opt some SSE/AVX ops. #109

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LATX, opt: Opt some SSE/AVX ops. #109

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7613d3b
LATX, opt: Opt maskmov ops.
phorcys Jul 23, 2025
a162646
LATX, opt: Opt VMOVMSK{PD,PS}
phorcys Jul 23, 2025
04d2850
LATX, opt: Opt vpackuswb, vpackusdw
phorcys Jul 23, 2025
4cbf46f
LATX, opt: Opt PSHUF{LW,HW} VPSHUF{LW,HW},VPSHUFD,SHUFPS,VSHUFPS
phorcys Jul 24, 2025
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46 changes: 15 additions & 31 deletions target/i386/latx/translator/tr-simd-mov.c
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Original file line number Diff line number Diff line change
Expand Up @@ -158,30 +158,22 @@ bool translate_maskmovq(IR1_INST *pir1)
IR2_OPND mask = ra_alloc_ftemp();
load_freg_from_ir1_2(src, ir1_get_opnd(pir1, 0), IS_INTEGER);
load_freg_from_ir1_2(mask, ir1_get_opnd(pir1, 1), IS_INTEGER);
IR2_OPND zero = ra_alloc_ftemp();
la_vxor_v(zero, zero, zero);
/*
* Mapping to LA 23 -> 30
*/
IR2_OPND base_opnd = ra_alloc_gpr(edi_index);
IR2_OPND temp_mask = ra_alloc_ftemp();
la_vandi_b(temp_mask, mask, 0x80);
IR2_OPND mem_mask = ra_alloc_ftemp();
la_vseq_b(mem_mask, temp_mask, zero);
la_vnor_v(temp_mask, mem_mask, zero);
IR2_OPND mem_data = ra_alloc_ftemp();
IR2_OPND xmm_data = ra_alloc_ftemp();
#ifndef TARGET_X86_64
la_bstrpick_d(base_opnd, base_opnd, 31, 0);
#else
if(!CODEIS64) {
la_bstrpick_d(base_opnd, base_opnd, 31, 0);
}
#endif
IR2_OPND mem_data = ra_alloc_ftemp();
IR2_OPND mem_mask = ra_alloc_ftemp();
la_vslti_b(mem_mask, mask, 0);
la_fld_d(mem_data, base_opnd, 0);
la_vand_v(xmm_data, src, temp_mask);
la_vand_v(mem_data, mem_data, mem_mask);
la_vor_v(mem_data, mem_data, xmm_data);
la_vbitsel_v(mem_data, mem_data, src, mem_mask);
la_fst_d(mem_data, base_opnd, 0);
return true;
}
Expand All @@ -203,17 +195,11 @@ bool translate_maskmovdqu(IR1_INST *pir1)
la_bstrpick_d(base_opnd, base_opnd, 31, 0);
}
#endif
IR2_OPND temp_mask = ra_alloc_ftemp();
la_vandi_b(temp_mask, mask, 0x80);
IR2_OPND mem_mask = ra_alloc_ftemp();
la_vseq_b(mem_mask, temp_mask, zero);
la_vnor_v(temp_mask, mem_mask, zero);
IR2_OPND mem_data = ra_alloc_ftemp();
IR2_OPND xmm_data = ra_alloc_ftemp();
IR2_OPND mem_mask = ra_alloc_ftemp();
la_vslti_b(mem_mask, mask, 0);
la_vld(mem_data, base_opnd, 0);
la_vand_v(xmm_data, src, temp_mask);
la_vand_v(mem_data, mem_data, mem_mask);
la_vor_v(mem_data, mem_data, xmm_data);
la_vbitsel_v(mem_data, mem_data, src, mem_mask);
la_vst(mem_data, base_opnd, 0);
return true;
}
Expand Down Expand Up @@ -534,14 +520,13 @@ bool translate_vmovmskps(IR1_INST * pir1) {
la_movfr2gr_d(dest, temp);
} else {
IR2_OPND temp1 = ra_alloc_ftemp();
IR2_OPND temp2 = ra_alloc_ftemp();
IR2_OPND dest_hi = ra_alloc_itemp();

la_xvmskltz_w(temp1,
ra_alloc_xmm(ir1_opnd_base_reg_num(ir1_get_opnd(pir1, 1))));
la_xvpermi_q(temp2, temp1, VEXTRINS_IMM_4_0(1, 1));
la_vslli_b(temp2, temp2, 4);
la_vor_v(temp1, temp1, temp2);
la_movfr2gr_d(dest, temp1);
la_vpickve2gr_du(dest, temp1, 0);
la_vpickve2gr_du(dest_hi, temp1, 2);
la_bstrins_d(dest, dest_hi, 7, 4);
}
return true;
}
Expand All @@ -558,14 +543,13 @@ bool translate_vmovmskpd(IR1_INST * pir1) {
la_movfr2gr_d(dest, temp);
} else {
IR2_OPND temp1 = ra_alloc_ftemp();
IR2_OPND temp2 = ra_alloc_ftemp();
IR2_OPND dest_hi = ra_alloc_itemp();

la_xvmskltz_d(temp1,
ra_alloc_xmm(ir1_opnd_base_reg_num(ir1_get_opnd(pir1, 1))));
la_xvpermi_q(temp2, temp1, VEXTRINS_IMM_4_0(1, 1));
la_vslli_b(temp2, temp2, 2);
la_vor_v(temp1, temp1, temp2);
la_movfr2gr_d(dest, temp1);
la_vpickve2gr_du(dest, temp1, 0);
la_vpickve2gr_du(dest_hi, temp1, 2);
la_bstrins_d(dest, dest_hi, 3, 2);
}
return true;
}
Expand Down
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