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Chip Conformance Scoreboard

Generated by chip_conformance_ratchet. L0 estate · L1 +registers-vs-silicon · L2 +behavior.

Reg match = verifiable cold-reset registers reproduced. "Excluded" = registers a cold model can't reproduce from a warm capture (calibration / clock-gated / boot-console / live status); see dynamic_excludes. A mismatch outside the excluded set is a real model gap.

Chip Level Estate Peripherals Reg match (verifiable) Excluded Behavior gate
esp32c3 L2 39 380/402 (94%) 190 firmware_survival::test_esp32c3_demo_survival
nrf54l15 L1 28 firmware_survival::test_nrf54l15_zephyr_survival
esp32 L0 14
esp32s3 L0 10
esp32s3-zero L0 17
stm32f401cdu6 L1 45 onboarding-stm32f401cdu6
stm32f411ceu6 L1 46 tier1::stm32f411
nrf52832 L1 16 firmware_survival::test_nrf52832_demo_survival
nrf52840 L1 49 firmware_survival::test_nrf52840_demo_survival
nrf5340 L1 20 firmware_survival::test_nrf5340_zephyr_survival
rp2040 L1 21 firmware_survival::test_rp2040_demo_survival
stm32f103 L1 31 stm32f1_exec_oracle
stm32f401 L1 21 firmware_survival::test_stm32f401_blinky_survival
stm32f407 L1 32 firmware_survival::test_nucleo_f407_smoke_survival
stm32g474re L0 20
stm32h563 L1 37 firmware_survival::test_stm32h563_demo_survival
stm32h735 L1 29 tier1::stm32h735
stm32l073 L2 42 55/55 (100%) 5 firmware_survival::test_nucleo_l073rz_smoke_survival
stm32l476 L1 58 firmware_survival::test_nucleo_l476rg_demo_survival
stm32wb55 L0 20
stm32wba52 L0 19
mkw41z4 L1 20 firmware_survival::test_kw41z_smoke_survival