These two reports are the authoritative answer to "what is modelled and how well is it validated." Both regenerate from the chip definitions + real CI runs and are auto-committed nightly — they do not drift:
- Chip conformance scoreboard — per chip:
conformance level (L0 estate · L1 +registers-vs-silicon · L2 +behavior),
the number of modelled peripherals, register-match % against silicon
captures, and the behavior gate test. Generated by the
chip_conformancetest fromconfigs/chips/*.yaml; refreshed + committed bycore-nightly.yml. - Tier-1 validation matrix — per chip ×
per subsystem (clock/gpio/uart/timer/dma/irq/i2c/spi/adc/pwm/wdt/rtc):
pass / partial / not-modelled, each cell linking the CI run that produced it.
Generated by
tier1-matrixnightly.
The per-board
docs/boards/*.md"Status at a glance" tables are hand-maintained prose snapshots — treat the two scoreboards above as the source of truth when they disagree.
The core-coverage-matrix-smoke.yml workflow runs a deterministic smoke matrix
over the executable targets and publishes a scoreboard artifact on every run:
coverage-matrix-scoreboard/scoreboard.mdcoverage-matrix-scoreboard/scoreboard.json
Both are summarized in the GitHub Actions step summary. The hard gate: the executable deterministic targets must maintain a ≥80% pass rate, enforced in the workflow's scoreboard job. The per-run pass/fail numbers live in the artifact and step summary — this doc no longer freezes a snapshot of them.
- Matrix CI uploads per-target artifacts under
out/coverage-matrix/<target-id>/. - Matrix CI aggregates and publishes scoreboard artifacts via
scripts/generate_coverage_matrix_scoreboard.py. - Update this file when the Top-5 scope, thresholds, or status policy changes.
- Do not mark
greenwithout deterministic re-run evidence.
Per-chip, per-peripheral real-firmware validation: tier1-scoreboard.